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Sample & Hold in Labview

Hello,

 

Is there a simple way to realise Sample & Hold analog circuit: analog value is sampled and stored in variable on a transition of some boolean signal ... TRUE -> FALSE or vice-versa.

 

Thanks

 

Best Regards

 

Pavel

 

 

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Message 1 of 10
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Yes, yes there is.

 

Mike...

 

PS: Sorry, I couldn't resist. A good way is to emulate the operation of a sample-and-hold circuit in software is to store the number temporarily in a shift register or a functional global variable (FGV).  But it sounds like first you would do well to go through the LabVIEW tutorials that you will find online. 


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Message 2 of 10
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What do you mean by a Sample-and-Hold circuit?  As Mike says, you can make a software S&H circuit by sampling and then saving the result in a Shift Register.

 

Are you talking about wanting to sample multiple channels where the data are acquired at precisely the same instant?  Then you need S&H circuits on each input, triggered by the "Convert" signal (and having the actual conversion be slightly delayed to let the S&H "hold" work).  A/D boards used to include this additional circuitry as a matter of course, but I'm not certain that this is still the case.

 

Bob Schor

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Message 3 of 10
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You can use a Feedback node.  Right click and select show enable terminal.  When enable is true, the feedback node stores the new value and delays its output, when false it returns the last value.  This behavior is better described in the help.

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Message 4 of 10
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Thanks for feedbacks,

 

Here is my setups:

 

Setup 1

  • analog signal A - varies slowly
  • analog signal B - reference
  • when A > B, store A and keep it

Setup 2

  • analog signal A - parabola-shape behavior
  • when A(i+1) > A(i), store A and keep it

Certainly, setup 2 would require a shift register, but probably for setup 1 esxists more simple solution (e.g. ready-to-use Sample&Hold block in some of toolboxes ... I've serched already, but have found nothing ... possible my LabView installation isn't complete)

 

Thanks

 

Pavel

 

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Message 5 of 10
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Your understanding of LabVIEW is incomplete. A ready to use sample and hold is the shift register. It's really basic and not difficult to understand.
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Message 6 of 10
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Hi Pavel,

 

where's the S&H scenario in case A?

 

IF A>B THEN
  store A
ENDIF
Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 7 of 10
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Hi GerdW,

 

Almost as on the image below, where:

 

Input signal - signal A

Sample/Hold Control - output from comparator A > B

 

The only difference form image - Sample/Hold Control must behave as flip-flop - i.e. edge sensitive.  

 

Best Regards

 

Pavel

 

 

 

 

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Message 8 of 10
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This was my thought.  You just have to generate your sample and hold pulse.  Note the mechanical action behavoir on the sample button.

 

Snippet.png

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Message 9 of 10
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I think you and I may be thinking of different meanings for a Sample-and-Hold circuit.  Here's my pseudocode for how a S&H works:

  • There are two inputs:  
    • Input (which takes a voltage or value)
    • Hold (which is a Boolean, True to Hold Input and return it, False to pass Input through)
  • There is a single Output
  • If Hold is False, then Input is connected to Output, i.e. the Input value is "passed through"
  • When Hold goes from False to True, Input is "Held" internally (in a Shift Register).
  • While Hold is True, the Output comes from the internally-Held value

This circuit is trivial to build as a sub-VI -- you need a While Loop with True wired to the Stop Indicator, two nested Case Structures, two Shift Registers, and Input and Output Terminals.  Call one Shift Register "Input", the other "Held" (as they will store these values).  There are three scenarios:

  1. Held is False (the "normal" case).  Pass Input to the Output terminal, "remember" Held.  
  2. Held goes from Low to High.  "Remember" Input, "remember" Held, and pass Input to the Output Terminal.
  3. Held stays High.  We ignore Input, "remember" Held, and pass the Held value to the Output Terminal.

We can distinguish Case 1 from the other two by wiring Held to the outer Case Statement.  By comparing Held to "remembered" Held, we can distinguish Cases 2 and 3.

 

This should be able to handle both of the S&H Scenarios you outlined.  Write it as a sub-VI and it will take up very little space on your Block Diagram.  Give the sub-VI an Icon (perhaps text that says "Sample & Hold") and it will be self-documenting on your main VI.

 

Bob Schor

 

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Message 10 of 10
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