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Run FPGA VI.

Hi

 

I have a project in which i configure everything running a teststand sequence.

But i have a VI in FPGA target that i want to load automatically too (using PXI).

The actual condition is that i go to the folder, open the FPGA labview project, then go to "FPGA target", open the VI and run it.

 

¿How can i do this automatically from a VI? I want the VI to be running and show the front panel.

 

 

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Working with TestStand?  What I normally do is have a sequence that I can run in a separate thread.  In this new thread seqeunce, I just have my FPGA VI.  So once you have the FPGA compiled, you just configure the Open FPGA VI Reference to use your bit file and then you can interact with your VI through that reference.


GCentral
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"Not that we are sufficient in ourselves to claim anything as coming from us, but our sufficiency is from God" - 2 Corinthians 3:5
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Thanks by your response.

Yes Im using teststand, but Im doing tests trying to do it from a VI.

 

You mean something like the image attached?

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That is the guy.

 

What I do is I have a VI that controls the FPGA.  I send data to it from my test seqeunces using a queue.  So I run the FPGA and then wait for data to come into the queue.  Process the data that comes through the queue and do what interfacing with the FPGA I need to do.  I usually send the data back with a queue or notifier.

 

Another alternative would be to use an Action Engine to hold your FPGA reference.  You just need a case to open and run your FPGA, a case to close the FPGA, and then whatever other cases you may need based on what your interface looks like.


GCentral
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"Not that we are sufficient in ourselves to claim anything as coming from us, but our sufficiency is from God" - 2 Corinthians 3:5
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Hi.

I'm working again with this part of my application. Still cant run automatically my FPGA VI.

 

I would like to show the FPGA VI front panel, and start running it. Then open the host VI and run it.

 

What I have:

From the host VI, with the invoke method, the "RUN" FPGA VI returns an error if the FPGA VI is closed. If opened, I can stop it and run it again. (attached image)

 

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