01-09-2016 06:27 PM
Hi
I'm seeing repeated values in my measurements and trying to determine the cause
I'm reading a single analog channel from an NI 9201 module. In order to remove noise I'm averaging several samples using the DC and RMS Measurements VI (shown in 'FPGA Code.png')
An example of repeated values is shown in 'Comparison of Signals.png' for both the original and averaged signal
The sample rate of the NI 9201 module for a single channel is 500 kS/s, which I have also verified by measuring the sample rate (the code for this is also shown in 'FPGA Code.png')
On the RT cRIO target I am recording these values in a timed loop running at 500us using the 1 MHz clock of the cRio
For the DC and RMS Measurements VI I have tried several options, for example:
- 500 us measurement time, sample rate 500 kS/s
- 450 us measurement time, sample rate 450 kS/s
- 400 us measurement time, sample rate 400 kS/s
- 300 us measurement time, sample rate 300 kS/s
All of them give measurements that have repeating values in varying degrees, for both the original and averaged signals
Any suggestions?
Solved! Go to Solution.
01-11-2016 12:12 AM
Try using a DMA FIFO to losslessly transfer data from the FPGA to the RT. I suspect you're getting a stale reading from the Pressure control on the FPGA front panel when using the FPGA Read from the RT.
01-11-2016 08:04 AM
Hello phg,
you should definetly use DMA FIFO for transferring data from FPGA to RT Target. In this latter target, you can use queues for reading data (with the producer/consumer loops configuration).
Another suggestion is to put some timing in the acquiring loop iin FPGA code, this may help to not get repeated samples.
I hope my answer helped you,
kind regards.
01-11-2016 09:22 AM
Both answer helps, thanks
I'm currently trying to figure out how to transfer my measurements from the FPGA to the RT Target using a FIFO
I'm not doing this for datalogging purposes however, I have a control loop on the RT target executing every 500us that I want to take a measurement value from the AI on the FPGA every 500us
Could/should a FIFO still be used for this? Ie sending a single measurement value from the FPGA every 500us (or slightly faster) through the FIFO?
Thanks!
01-11-2016 09:41 AM
So you just want to read the value on AI every 500 us, is it correct?
In this case you should use a timing in the FPGA loop and then write the value to an indicator. Then, in the RT target you can read it using the proper invoke node.
In this case you have to be very careful to the timing of the loops.
Kind regards.
01-11-2016 10:09 AM - edited 01-11-2016 10:18 AM
That is correct
I have tried to implement this but I haven't been successful, here is what I have tried:
The FPGA and RT VI's are shown in 'FPGA Code.png' and 'RT Code.png'
The FIFO I made by right clicking the FPGA in the project manager, then clicking 'New -> FIFO'
I selected 'Target to Host - DMA', datatype 'FXP' and the rest was left to default ('Requested number of elements' is 1023 by default)
Then I dragged the FIFO into the FPGA VI and implemented the code shown in the figure
The wait is set to 400 uSec, for timeout (specified in ticks) I wasn't sure what to put and simply put 500
The channel I am trying to read is MOD4/AI1 and I am able to read from it without the FIFO.
However using the FIFO I simply get a "0" on the output on the RT VI, shown in 'Data Output.png'
Edit: I also tried setting the timeout to '600000' in the FPGA, still doesn't work
Any advice? Thanks!
01-11-2016 10:28 AM
Hey phg,
try to avoid the coertion during the fill of the FIFO in FPGA vi. You also put 0 as "Timeout" value in FIFO, both in FPGA and RT vi.
You should also put a control structure to verify that FIFO is not empty, firstly reading 0 elements, checking if "Elements remaining" is greater or equal than 1 and then reading 1 element from the queue. This will avoid you from reading empty queue.
Let me know if these advices solved your problems.
Kind regards.
01-11-2016 10:32 AM
Hi, thanks for the reply!
But how do I remove the coercion? I don't understand why it is being coerced, both should be in FXP as indicated by the grey color?
Thanks
01-11-2016 10:34 AM
Yes but you have to be sure that the type of fxp is the same (i.e. if they have the same number of bit for entire and floating part, if they are both unsigned..)
01-11-2016 11:15 AM
Thanks!
Any suggestion how I can determine the exact type of FXP my AI module is outputting?
When howevering over it with the help-function activated I see this:
see attached image: 'fxp.png'
What I need is 'word length' and 'integer word length'