Reduce peak voltage out of DIO96

[analog engineer]

The TTL levels and -1.5 v negative spikes out of the DIO96 interface card damage CMOS 3volt CPLD logic.

How can I reduce the peak positive and negative voltages out of the DO96 card to be compatible with CMOS 3 volt logic?

[unclebump]

Looks like you will need some external hardware interface chips. The only LVCMOS/LVTTL on the NI site is from PDA compact flash DAQ modules.

http://focus.ti.com/logic/docs/generalcontent.tsp?templateId=5985&navigationId=11408&contentId=4198