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Real-Time: issue reading FIFO from FPGA

Hello Shane,

 

thank you for the reply.

 

I think what you propose is in principle what I did: Use a sub-counter within the timed loop. I have only two (analog inputs) to interleave, so I made a bolean shift register. So at tick 1,3,5 ,... data from AI 0 is put into the fifo and at tick 2,4, 6... data from AI 1 is put into the same fifo. I use a case structure to do this. Clock rate is 20 MHz.

 

However, I get an error 91 saying that the data type of the variant is not compatible with the data type wired to the input. I'm flabbergasted and  have to figure out if this error is related to this or not.

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Ok. the actual problem that I have with the state machine approach is as follows (when compiling):

 

"Multiple objects are requesting access to a resource through a resource interface configured with the 'Arbitrate if Multiple Requestors Only' option, which is only supported in the single-cycle Timed Loop if there is only a single requestor per interface.

Remove the extra requestor(s), change the arbitration option if possible, or replace the single-cycle Timed Loop with a While Loop."

 

What "requestor" refer to is the 4 FIFO nodes I am using....

 

Attached is a screen shot for the false case (ticks 1, 2, 3, ...) and true (ticks 2,4,6,...). 

For now I use a while loop as proposed by the error message. When I will have more time I try to find a work around WITH the SCTL

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