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Hi

 

1) Can I do the calculation in the Host VI under RT target and only use the FPGA for reading input and writing on the output port?

2) Are there any issues of lack of resource or timing issues regarding to RT target?

3) If the answer of #2 is yes how can I simulate it before donlowding the program to the hardware?

 

Thanks

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@loghmani wrote:

1) Can I do the calculation in the Host VI under RT target and only use the FPGA for reading input and writing on the output port?

2) Are there any issues of lack of resource or timing issues regarding to RT target?

3) If the answer of #2 is yes how can I simulate it before donlowding the program to the hardware?


1) Assuming you can do the calculations fast enough in the RT, absolutely

2) It really depends on your control rate.  If you need really fast rates, then you are best doing it in the FPGA.  But you will have to worry about FPGA resources (gate usage, mostly).  If you need control rates in the 100s of microseconds or miliseconds, I see no reason why the RT couldn't keep up.  Going any faster I would start to question how complicated your control algorithms are before saying which way would be better.


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Thank you.

You mean that for processing rates more than 10 kHz RT couldn't keep up?

 

My sample rating is 1 kHz and the program is a FXLMS control algorithm which must be done between two samples.. 

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@loghmani wrote:

Thank you.

You mean that for processing rates more than 10 kHz RT couldn't keep up?

 

My sample rating is 1 kHz and the program is a FXLMS control algorithm which must be done between two samples.. 


It depends on the complication of the algorithm (ie, how much calculations is needed).  Now that I'm looking at your other thead, I see no reason why the RT couldn't handle it.  And at 1kHz, even less worried.


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What about the issue of fulling the resources in RT? Is there any kind of such issues regarding to RT?

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RAM?  Harddrive space?  Maxing out your CPU?


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