02-21-2013 08:36 AM
Good Afternoon
I'm developing a project that consists in acquisition of voltage signals using a CRio 9074, with four modules 9215. I've developed a code based on the examples provided by NI, they are in appendix, but when i define my sample time of 10usec (100KHz), to adquire a sine wave with a frequency of 100Hz, with 1000 samples, my waveform graph should give me one period of the sine wave with 100Hz. Instead the waveform graph is give me a aproximatly 10 periods od the same sine wave. Can someone, explain me why i have a factor of ten when i should had one period instead, because this factor is present if i change the sample time and/or the number of samples. In appendix i've send pictures of my FPGA and HOST code, with a execution to try adquire a sine wave with 100Hz with a sample time of 10usec( 100KHz) with 1000 samples.
Thanks in advance
03-01-2013 08:30 AM
Hi,
Have you find a solution since you've posted this forum? I agree with your calculation, could you post your code so we can have a look?
Thanks,
03-02-2013 06:07 AM
Hello
I've solved the problem of acquisition time, using the code that i put in appendix. I've made some tests, to validate the code, and seems to work fine. I'm now try to understand the reason why two different modules aren't synchronize. I've put the same signal in two different modules, and they have one sample delay between both signals, and i'm trying to understand why. If you have any suggestion it would be much appreciated.
Best regards