02-17-2016 08:22 PM
Hi,
I am received a .vi from a software supplier and I need to make some modifications. In first, I am experiencing a very high jitter (RT Timed Loop period = 3000us, with the 90% percentile as high as 3900). The task is simple, read 8 channels from the FPGA, do a trigger and record the data to a tdms file. Do anyone has a tip or a solution for this problem?
Some ideas that I have
- There is some queues using the default LV FIFO, not the RT FIFO. But the limitations of the RT FIFO makes me think it's not worthy to change that.
- The .VI uses local variables, change to global or shared?
- The cRIo (NI 9075) dont have a local clock, every time it restarts the time is set to 1973, I make a low priority loop that set the clock every 10min exept if the Time Loop is recording data. Maybe it is adding jitter too
Tks
02-18-2016 02:24 AM
Hi,
Is it jitter (i.e. sometimes on time and occasionally late) or is it a CPU problem (runs consistently over time or spikes when the CPU usage spikes? this can make a difference as obviously the CPU one is about reducing what you are doing vs jitter is fixed by changing how you are doing it.
Looking at possible sources of jitter that I can see there are a couple but you appear to have disabled most of them:
This is all I can really see from a jitter perspective. I would watch the CPU usage while this is running and my instinct would be to be suspicious of that. In particular are you getting spikes when the 10 second loop runs to write data to file that might be causing some strange behaviour although your loop should take precendent due to the priority system.
02-18-2016 10:24 AM
I agree with James about checking the CPU usage. The closer you are running to 100% usage, the more variance you will see in execution rate.
I don't know how you are setting the system time every 10 minutes, but I would only advise changing the cRIO time at the very beginning of your application. After you set the current time use something like TimeSync to make sure your times don't drift. I have seen some very strange behavior for timed loops when the system time changes too much.
02-18-2016 01:45 PM
Tks James and Jacobson.
I made a test and the cpu usage is about 88%. I attached 2 files, the first is the sampling time of a "normal" operation, with a bad jitter. The second is one with a huge problem, some samples getting 35ms to complete.
My problem with this cRio is that it is in a remote field subject to constant power outages.