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RT FIFOs and data logging

Hi

I am trying to use my RIO FPGAs and DMAS, FIFOs etc to read some analog inputs and log the data in a tdms file. I have followed a basic labview example yet my code is not working as it should; on clicking 'run' an error (61003) is obtained from the fifo read and the program stops. Can anyone see an obvious reason why?

 

The FPGA Code:

 

CAP 2.PNG

 

and the RT code

CAP 1.PNG

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Hi Boileroo

 

It's worth checking that your FPGA reference isn't set to 'Open and Run' instead of just 'Open, since when you reach the 'Run' node in your code it would return error 61003 as your have described.

It's also worth recompiling your FPGA VI just to make sure nothing is corrupted there.

 

Kind Regards

Chris | Applications Engineer NIUK
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alas no unfortunately not, that was my thought too!

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Could you attach your actual VI/project so I can try to run it here?

 

Kind regards

 

Chris | Applications Engineer NIUK
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I'm afraid I cant! My place of work has very strict rules governing the upload/download of files. Sorry!

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No worries.

The error code relates to already having the FPGA reference open, so somewhere along the lines it's getting opened twice (attempted).

To be certain: 

1) 'Run the FPGA VI' is unticked on 'Configure FPGA VI reference'

2) 'Run when opened' is unticked on the FPGA VI properties, under the category execution.

3) Have you tried enabling 'Wait until done' (T) on the Run node?

4) Alternatively try removing the Run node, since the error implies that it's already running.

 

As an aside I notice you're also missing FIFO.Stop from the DMA FIFO example.

 

Kind Regards

Chris | Applications Engineer NIUK
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thanks a lot. with the above things I finaly was able to get it all to work as it should!

I have a couple of quick questions regarding the use of DMA FIFOs. It seems to me that the variables we have control over in this sort of instance are:

 

-The speed of the FPGA Loop. In this case wish to sample at 500 kHz so this is 2 usec

-The size of the FIFO buffer, both on the RT system and the FPGA

-The number of elements read from the FIFO with each RT iteration

 

Is anyone able to explain to me how to go about sizng these things? I have managed to get it working through arbitrary tweaking of the above parameters but am not happy that I understand how it all works!

 

 

Many thanksCapture FPGA.JPG

Capture RT.JPG

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