Pulse generation PCI-6220

[RobMotz]

Hi there,

I´m an absolutely newbie to labview and hope to get some advices as I´m completely stuck at the moment.
I´d like to generate variable TTL pulses to 3 different lines. Since the PCI6220 card only has two counters I´ve to go for the normal hardware correlated DIO lines.
For now I´d be happy to see it working just for one line as follows:

__|   |________|           |_ ...

I´ve to be able to set the pulse width of the high time for the first and the second pulse as well as the two different low times. This scheme should furthermore than be repeated n times. Thus having 5 variables, the length of the pulses in ms: 'Low1','High1','Low2','High2', and the number of repetitions: 'n'.
I may be horribly wrong with this, but I think working with the duty cycle doesn´t work for that application, does it?
Assuming I use the frequency generation of a counter as a sample clock to my pulse generation, it seems rather simple taking for instance 'High1' corresponding pulses of the counter clock to generate the 1st pulse then 'Low2' pulses for the subsequent low pulse and so forth. Could anyone give me a hint to do so, or are there better/other ways how to achieve this? Are there eventually vi's available I could start with (haven´t found proper one´s in this forum nor in the Labview implemented library)?

Many, many thanks in advance for any help!!

Robert

[Christian Mergl]

Hey,

Maybe the following example of a PWM for an M-Series (out of devzone) will give you some hints or could be used to build up on it.

Christian

[RobMotz]

Hi Christian,

thanks for the reply. I was actually looking intensively at this example a while ago, but frankly I do not see how this could be turned into my application.
The thing with the duty cycle is that it generates always the same (adjustable though!) pulse width for the high signal. The problem I´m facing is to generate a sequence with two distinct pulse width´s.
And I don´t see how I could achieve it with the duty cycle example. Or can it be done?

Thanks in advance, any help is much appreciated!

Rob

[Kevin_Price]

I don't have LV handy and can't look at the example.  Also not much time.  Just a couple quick notes:

1. Since you know the pulse specs ahead of time N*(L1,H1,L2,H2), it certainly should be possible to use correlated DIO on an M-series board.  Crude example: let's round all time to the nearest microsec and then use a counter to generate a 1 MHz sample clock.  You just generate an array containing quantity L1 of "F" followed by quantity H1 of "T", then L2 "F"'s and H2 ("T"'s).  Then append this array on itself repeatedly until you've got N total patterns.

2. Later when you try to generate 3 independent outputs, you'll need to be careful about the timing resolution.  If your first signal's times always rounds to the nearest microsec, but the next one rounds to the nearest 0.1 microsec, you'll need to recalc the first signal's array to be in terms of 0.1 microsec resolution.  In the end, ALL 3 SIGNALS will share the same counter sample clock timebase.  The pulses that transition less often will just require you to define longer runs of constant "T" or "F" values.

-Kevin P.

[RobMotz]

Hi,

thanks so much for the input.
I tried exactly what you recommended but I seem to fail finally getting some output at the DO line. As you can see in the attached vi, I use the counter's frequency output as sample clock.
My next thought, perhaps a naive one, was to create an array with ones and zeros which determine the high and low time of the pulse (total length 1000 pulses, 800high, 200low). I see the sample clock but nothing at the DO line. Any idea what´s wrong in the code??

Any input is very much appreciated!!

Thanks and best regards!

[RobMotz]

I´m lost...
No one with an idea?

Rob

[Christian Mergl]

Attached you will find another example...or the application as I understood your definition...

[Kevin_Price]

Rob:  I looked at your example earlier when I was near my LV machine.  From memory:

1. I think I recall that you specified PFI 2 as the sample clock source for the digital task while using CTR 0 to generate the clock.  According to this doc, the default output pin for CTR 0 is "terminal" 2.  However, that does NOT turn out to be another name for PFI 2.  Rather, terminal 2 is designated as PFI 12 as can be seen here.   (This stuff is also visible in MAX when you select your device, right-click and choose "device pinouts").

2. I recall you used a U32 array version of DAQmx Write. You may need to use the U8 version on your 6220 board.  Also, the init values you wrote before the loop alternate between 255 (all bits high) and 0 (all bits low).  The values you write inside the loop alterate between 1 (LSB high, all other bits low) and 0 (all bits low).

3. You defined the digital task for finite generation, filled its buffer before the loop, then attempted to keep overwriting it inside the loop.  These are not mutually consistent.  If you want finite generation, fill once only.  If you want continuous generation, it'll take some care not to overwrite too soon.

4. Minor nit: It may not matter in your app, but often its best to start up the digital task before starting the counter task that generates its clock.  You can accomplish this by simply routing the error cluster from the digital task's DAQmx Start up to the counter task's Create Virtual Channel.

I'm not near LV now to look at the recent example from Christian M.  Hope it suits your needs...

-Kevin P.

[RobMotz]

Hi Christian,
thanks for the example. That looks very promising indeed.
However, I always get the error message d1802 (dt values not equal in Append Digital Samples VI) in the 'ConfigPulse.vi'.
Couldn´t solve the issue with hints given under: http://digital.ni.com/public.nsf/websearch/C41966093C3D030F86256FF8007F8BF5?OpenDocument
Any pointers how to get the example code running?

Thanks so much for the help!

Rob

[Christian Mergl]

Hey,

I'm wondering about this error but attached you will find the ConfigPulse.vi modified according the KB you posted.

Christian