Pre trigger problems

[MightyEKA]

Hello,

I'm having some issues with my project. I can't figure out what's wrong. The project is to build a FPGA-target which uses a trigger to start sampling data and it also needs to have pre/post trigger functions, but it just won't trigger when it's supposed to.

I'm attaching my program.

Regards,

Tim Jansson

(It seems that I managed to double post this thread again. I apologize and hope that this won't cause too much problems)

Message Edited by MightyEKA on 11-23-2009 01:05 AM

[MightyEKA]

I'm quite stuck acctually. Right now, my FPGA works...bad. It triggers but now I'm using 3 FIFOs (one local) and I don't think this is neccesary. My host program is even worse, and it doesn't even uses the trigger.

Don't even bother to look at the Front Panel! 😉

Tim

[Norbert_B]

Tim,

i am sorry. But reading your posts and looking into your code, i do not understand, what you are trying to achieve in the first place.

I suggest you to describe what your task is, what is the setup (without any code) and if there are any restrictions. 

hope this helps,

Norbert 

[MightyEKA]

Thanks for reply!

I'm sorry for being confusing! I manage to solve the problem and I understand that you were confused by my previous code. It confused me as well. I got things mixed up, and I made things much more complicated than it should be, but the problem is solved and the result is a simple code

Sorry for the inconvenience!

Regards,

Tim

Message Edited by MightyEKA on 11-25-2009 03:48 AM

[MightyEKA]

Is it possible to send a huge amount of elements (I might need to sample 30 seconds) through DMA even though my FIFO size is only ~2000 elements? Is it possible to "wrap" these up in blocks and send the blocks as elements? Or do I have to make a new code from the beginning?

Regards,

Tim

[MightyEKA · Accepted solution]

Never mind! I solved it!

[cdonc]

Hello

Is it possible for you to upload the fixed VI?