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Possible FPGA propagation delay on SPI code? Requesting confirmation.

I have a SCTL VI that uses the FPGA of an NI 9076 to act as a SPI master. It uses NI 9401 (8CH DIO cards) to drive the CS, CLK, and data lines. The issue I encountered was that reads I was getting on my MISO line was shifted to the right 1 bit. After much troubleshooting (on and off for over a month), I determined that the read of the MISO line actually appears to be delayed by 6 clock cycles. To determine this, I tied a spare digital out (labeled as MOSI3 in my VI) directly to the digital input that samples MISO (0). The results are in the attached image. As you can see, the difference between actual MISO and SMISO (sampled MISO) is six clock cycles. This would account for the 1 bit shift. Would somebody kindly confirm that what I'm seeing is some combination of propagation delays between sampling and then outputing to this pin and possibly explain why it occurs over so many clock cycles. All of the other threads I have read have indicated that this delay should be 1-2 cycles maximum, while I am seeing 6. It would be helpful for me to understand why this is occuring, and how to correct it (if there are any other means than delaying when I sample). I need to maintain determinism and I'm reluctanct to delay my sampling as it would require a fair amount of code reworking to ensure determinism is maintained. The sub VI that drives my master is also attached.

 

Also, if helpful, the bit A6 is where MISO is sampled (rising edge of SCLK) to confirm that the actual MISO line is properly timed. Please neglect bit A5 as this was used for other troubleshooting.

 

Thanks for the support!

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Also, in the attached VI, it shows the DO MOSI1, MOSI2, and MOSI3 being used twice in one case. In my actual version I ran, the elements on the left were removed. I did a few stages of "undo" between running my debug code and discovering the issue. Please treat these FPGA nodes as if they weren't there. Thanks!

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ScottKenyon,

 

I've taken a look and it's hard to tell what might be causing this. In doing some research, it seems there are some SPI FPGA LabVIEW examples out there. It may be helpful to look at these examples for comparing code. I included a link below to one of our White Paper articles on this topic. Maybe you've seen it or are implementing this already, but in case you weren't, I figured it never hurts to point it out.

 

http://www.ni.com/white-paper/9117/en/

 

Is there any sort of pipelining or feedback nodes going on that might delay the cycles before valid data is output?

 

 

Robert B
RF Product Support Engineer
National Instruments
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Hi USBarnes,

 

I appreciate your response. I have seen that SPI example, but have not downloaded the VI and probed into it deeper. I certainly will look into that this week to see if it offers a clue in this delay I'm seeing.

 

After, posting this thread, I "fixed" the issue by sampling the MISO line after 4 clock cycles had passed the from the rising edge of SCLK. This works, but is not my preferred solution as I don't fully understand the implications of this technique on my design. Again, I will probe into the example and hopefully gain some insight.

 

Just for giggles, I wrote the attached VI to check out whether these delays were a result of my code specifically, or inherent to the FPGA. The resulting image shows that each read of an FPGA node results in a delay of roughly 150 nsec, or 6 clock cycles, consistently. I simply tied my first DO to a boolean control, then on my board, tied this to my first DI. Then I wrote this DI to the next DO, and so on. I guess this confirms the delay, but I'm still interested as to whether there is a means to eliminate it or if it's just something that must be dealt with.

 

Thanks,

Scott

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Also found this, almost identical issue: http://forums.ni.com/t5/LabVIEW/FPGA-I-O-pin-delay/td-p/853148

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I've now read some information on sync register propagation delay: http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_sctl_and_synchro/#synchregzer...

 

I changed the registers to 0 for each line, but the delay persists...

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