LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

Polynomial Evaluation in FPGA

Solved!
Go to solution

Hi all,
I am currently facing a problem. I want to evaluate an 6 order polynom in the FPGA (Actually this function will be part of a larger VI). Here is what I implemented :
Polynom.PNGTab Coef contains the 7 following coefficients (coming from the RT) :

2734.91

53.4378

-2.02666

0.0463295

-0.000588338

3.71736e-06

-9.06681e-09

 

When I sent this VI in the Compile Worker 2013, I get the following error :

LabVIEW FPGA:  The compilation failed due to resource overmapping.  

The FPGA VI does not fit on the FPGA target because the VI requires more resources
than are available.

Suggestions for eliminating the problem:
  * Reduce the amount of logic in the VI
  * Reduce the number of multiplications, FIFOs, and/or amount of memory on the block diagram
  * Reduce the number of objects on the front panel
  * Change arbitration settings
  * Use Timed Loops instead of other loops
  * Use Timed Loops for resource-intensive sections of the block diagram that
    do not require any looping

 

I don't know how to solve this problem... Any Idea ?

Thanks a lot !
Tom

 

0 Kudos
Message 1 of 5
(3,934 Views)
Solution
Accepted by topic author TomVM1

What if you did this in a For Loop?  Two shift registers, one to accumulate the multiplications of the X value, the other to accumulate the additions of the polynomial.

Message 2 of 5
(3,931 Views)

Hi,

 

additional note: what if you did this using FXP arithmetics?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
0 Kudos
Message 3 of 5
(3,925 Views)

Yup... It works perfectly ! Thanks a lot ! Don't know why I didn't though about that before...

Anyway, thank you !

0 Kudos
Message 4 of 5
(3,917 Views)

@RavensFan wrote:

What if you did this in a For Loop?  Two shift registers, one to accumulate the multiplications of the X value, the other to accumulate the additions of the polynomial.


RavensFans is onto something. There are a pretty limited number of multiplication resources available on the FPGA so you need to find a way to reduce the number of these nodes on the block diagram. The easiest way is to find a way to use a single multiplication and a For loop (e.g. build array, multiply, index array) - this uses less FPGA resources but your operation will take more clock cycles to complete (e.g wouldn't work in a single cycle timed loop).


LabVIEW Champion, CLA, CLED, CTD
(blog)
Message 5 of 5
(3,905 Views)