PXI 5122 Ext Clock Questions

[AustinMcElroy]

I am working on a project that requires the ext. clock (100Ms/s on a 5122) and a signal hand-off.  Signal 1 is 32MHz, and Signal 2 is 32MHz +- 100,000Hz.  If I am feeding in Signal 1, what is the minimum and maximum times I have to kill signal 1 and input Signal 2 so that the card doesn't crash.  In other words, the jitter parameters on the PXI 5122 clock.  I cannot find this information anywhere.  If I had to guess, the minimum time would be 1/105MHz = 9.5ns and the max would be 1/30MHz = 33.3ns.  The 30MHz and 105MHz comes from the PXI 5122 data sheet.

Also, if the hand-off were made smoothly withing the jitter specification times, would the clock crash due to the change in frequency between the 2 signals?

Thank you for your time,
Austin McElroy

[minh.tran@ni.com]

Good morning Austin,

Thanks for contacting National Instruments with your issue, we'll try our best to solve it for you as quickly and efficiently as possible.

I'm going to have to contact R&D about this specification.  There are some that might get us close, such as the fact that the PLL Reference Frequency has to be accurate to +/-50 ppm (page 14 of (http://digital.ni.com/manuals.nsf/websearch/5D8BAB258130779686256FA800691AAA)) and that the sample clock delay range is 1 sample clock period (Page 13), that I could postulate on, but I'd rather get the definitive answer.

One point of helpful clarification would be whether you're using the external clock for the reference clock or sample-clock timebase. 

I will let you know as soon as I hear anything from R&D.

Sincerely,

Minh Tran

Applications Engineering

National Instruments