LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

Only 3 of 32 Block RAMS used and still showing error

Solved!
Go to solution

Hi

 

I'm working on counting of Photons as they arrive at DIO0. Cutting short, there's a lot of data coming and I need to send it to the host as fast as possible. For this, I have used a Target-scoped FIFO in a single-cycled timed loop and another Target to Host FIFO which takes data from this Target-scoped FIFO and send it to the host.

According to the analysis I have done, I need target-scoped FIFO to be 600,000 Boolean elements deep. This should be possible given I'm using virtex-5 LX30 FPGA which has 32 (36kbits each) Block RAM. However, when I increase the requested number of elements in this FIFO, the compilation doesn't happen saying the code doesn't fit into FPGA while it still shows that only 3 of 32 Block RAM have been used.

I have tried searching a lot about any limitations on FIFO but I haven't found any.

Please help me out here the earliest.

I have attached the VI file and the Xilinx log sheet of compilation.

There are 6 FIFOs in this project:

Host to Target DMA (I32 elements, 1023)

Target to Host DMA (Boolean elements, 2000)

Target to Host DMA U32 (U32 elements, 500)

Target-scoped DMA Write (I32 elements, 16000)
Target-scoped DMA Count (Boolean elements, 108000)
Target-scoped DMA Count U32 (U32 elements, 500)

Download All
0 Kudos
Message 1 of 4
(2,863 Views)
Solution
Accepted by topic author anchal.physics

There is a bug in the Xilinx compiler that not all types of instantiated block rams are reported.

 

I have made a similar find before.  http://forums.ni.com/t5/LabVIEW/FPGA-Block-Ram-FIFO-Resource-usage/m-p/2978897/highlight/true#M85572...

 

As such, simply ignore the statistics fromt he compile, they are wrong.

 

Block RAM is not addressable as 36k x 1 bit, it has either 36bit width or 72 bit width.  This means that 1 bit, 2 bits, all the way up to 36 bits all fill one cell of the block RAM.

 

As such, your usage will be 600k x 36 bit which gives way more than what you have assumed to be 1x60000 bit storage trequirement.

 

1x600k fits in 32x36k Block RAM (600kb required, 1Mb available)

but the reality is that

36x600k does not fit in 32x36k block Ram (21Mb required, 1Mb available).

 

If you can, try bit packing the booleans into a 36-bit FXP before writing to the Block RAM you will significantly improve things.

Message 2 of 4
(2,826 Views)

Thanks a lot for your solution. Is there a way to know whether the Block RAM is addressable as 36bit width or 72 bit width?

 

 

0 Kudos
Message 3 of 4
(2,794 Views)

The width is determined by the compiler. If you write more than 36 bits at a time, it will be 72 bit, otherwise it stays 36 bit.

0 Kudos
Message 4 of 4
(2,768 Views)