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NI 9223 1MS/s continuously

Good morning everybody,

 

i'm trying to get the maximum sample rate of 1 MS/s with the NI 9223 module (with a crio 9074) to use it for an optical particle counter. I have read many posts in the community (of course) and tried to solve the problem on my own but i think it's time for a little help.

Back to the topic: the fpga is stopping after a one period of sampling and so the host-vi and it's not possible to run it continuously. I'm using the "user controlled sampling"-example code for the 9223. Anybody an idea? Ist is possible that the 9074 is the problem?

 

greetings

 

Fabian

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Hallo Frank Fabian,

 

why does the FPGA stop? Is there a reason to stop the FPGA after one period?

 

Why do you use "user controlled sampling" when you want to achieve a fixed sample rate of 1MS/s?

 

Can you attach your VI(s)?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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GerdW wrote:

Hallo Frank Fabian,

 

Hi Gerd!

 

why does the FPGA stop? Is there a reason to stop the FPGA after one period?

 

-> I don't see any reason.

 

Why do you use "user controlled sampling" when you want to achieve a fixed sample rate of 1MS/s?

 

-> The 9223 "getting started" example says that the standard IO nodes cannot achieve the maximum sample rate and refers to the the "user controlled"-example.

 

Can you attach your VI(s)?

 

-> Sure, but it is in principle only the included example.

 

Thank you for your quick response.

Fabian

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Hello Fabian,

 

My name is Alexander Beckmann, I'm an applications engineer working for NI Germany.

 

I tried the example for User-Controller IO Sampling on a 9074, but I haven't looked at your VIs, yet.

 

It is true that you need to use user controlled sampling if you want to reach 1MS/s. IO-Nodes can only reach 300kS/s according to this KB: http://digital.ni.com/public.nsf/allkb/5250C3AAE0CBAAE68625777F0072438E

 

The VIs in the example are made so that they acquire a fixed number of samples. If you need to acquire more data you can put a loop on the FPGA VI and wait for the IRQ from the Host VI for every acquisition period. You will also need to add a loop to the Host VI, maybe with an event structure, depending on what you want to do. However, the cRIO-9074 does not appear to be fast enough to handle 4 channels of continuous acquisition at 1MS/s. I get a timeout on the FPGA VI if I'm trying to acquire more than 6000 samples at once. You can get the amount higher if you increase the FIFO buffer, but the memory on the 9074 is quite limited.

 

I hope this helps, feel free to ask if you have more questions.

Alex

Applications Engineering Intern, NI Germany
Certified LabVIEW Developer
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Hello Alex,

thanks for your quick answer ans also a "sorry" for my late response. I was very busy with the "additional" hardware.

Broadly speaking your answer solved my problem. I was using an NI 9222 bevor and just replaced the the vi without having a closer look to the fpga code. So sorry for that.

 

I'm using the host-vi now as a subvi in a loop with an iteration timer. It says that every sampleperiode of 5000 sample et 1MS/s takes about 160 - 200 ms (i'm getting the timeout at 6000 samples too). Which means, that the "deadtime" without sampling is about 40 times longer than the samplingtime. Is it possible for you to verify this or do you habe some ideas to improve the loop timing?

 

I added my host-vi which additionally contains a network-stream "startpoint". Basically that's all what has to be done at the crio.

 

regards

Fabian

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Hello Fabian,

 

it is difficult for me to check this without having all of your SubVIs. But I think 200ms is too long. 5000 samples at 4 bytes (double precision) is 20kB. This should not take 200ms to process.

 

I found this example which tests streaming data from FPGA via RT to Windows.

http://www.ni.com/example/30919/en/

It streams 24 channels of U32 values. By default it is running at 800 ticks, that means 50kS/s. On my 9074 this gives a CPU usage of 85%. 50kS/s at 24 channels and 4 bytes is about 5MB/s which is much more than what you are doing. Maybe this example can help you. It is optimized for throughput, not for determinism.

 

Best regards,

Alex

Applications Engineering Intern, NI Germany
Certified LabVIEW Developer
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Hi All,

 

I'm trying to measure a 1uS current pulse in a period of 10uS with the NI9223.

Also started with the "user controlled sampling" example.

Put a loop arround the FPGA and Host VI.

But it does not run at max speed.

Did some testing (you can see some nodes to a NI9401 to check loop activities, and FPGA user LED to see if it's stuck).

I came out that it blocks on the "wait for IRQ" at high speeds.

Is there an update limit for these IRQ's, or should they be able to run up to 40MHz?

 

I'm using a Crio 9045, and only 1 analog input of the 9223.

 

Need some advise....

 

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