NI 7966 - NI 6584 Half Duplex RS485 communication problem

[profx1288]

Hi,

I have a RS 485 communication problem with NI 6584 half duplex adapter. Let me give some information about my system, and then I will talk about what my problem is and what I have tried to overcome the problem. I have a PXI chassis, which has an operating system of LabVIEW RT. The PXI chassis is controlled with a desktop PC. There is a NI 7966 FPGA card plugged in the PXI. A NI 6584 RS485 half duplex card is plugged on the NI 7966 card. My aim is to communicate three different electronic cards via RS485 protocols at different data rates. The cards communications speeds are 4Mbit/sec, 4Mbit/sec, and 8Mbit/sec. I have no problem when I try to communicate the cards separately.

I also want to give brief information about my LabVIEW code. At first, I have developed an FPGA code which contains some parameters, which are generation clock divider, acquisition data with, start-stop bit counts etc., about communication. For different baud rates, different clock frequencies are generated. For 4 Mbit/sec communication 32.04MHz and for 8 Mbit/sec communication 82.67 MHz clocks are generated. In my application, two reading processes should be done at 4 Mbit/sec and a read-write process should be done at 8 Mbit/sec. So, the FPGA source code composed of three main parts, which are two reading parts at 4 Mbit/sec and a read-write part at 8 Mbit/sec.  After the FPGA source code is compiled, the created bit file is integrated to main vi. In the main VI, first the FPGA is opened and the created bit file is chosen, then two different timed while loops are created. One loop contains the FIFOs, which are used to receive the data from two cards at 4 Mbit/sec, and another loop contains read and write FIFO blocks to read and write at 8 Mbit/sec. At the same time, different processors are assigned for different loops.

Here is my problem. I want to communicate the three cards at the same time. In the main vi, when I disable the loop which is used for 8 Mbit/sec communication, 4 Mbit/sec communication works well. Similarly, when I disable the 4 Mbit/sec communication loop, 8 Mbit/sec works well. However, when I enable the two loops, in other words, when I try to communicate with three cards at the same time, a problem occurs. During each run, the 4 Mbit/sec communication does not work, on the other hand, 8 Mbit/sec part works well. What could be the reason and how can I overcome this issue?

I think using the different clocks, which are 32.04 MHz and 82.67 MHz at the same FPGA bit file, causes the problem. Based on the thought of this issue, I have tried some ways to overcome the problem. First, I have used the same clock rate, which is 82.67 MHz for two data rates. At this solution, I have adjusted the generation clock divider, acquisition clock divider, start-stop data bits, sample bit count parameters according to the 82.67 MHz. However, it did not work. Second, I have generated two different FPGA source codes and bit files. One of them is for communicating at 4 Mbit/sec while the other one is 8 Mbit/sec. At this trial, there are two “open fpga” block is added to main vi. And then, two bit files chosen and the reference outputs of the “open fpga” blocks are sent to time different timed loops.

Am I clear enough, what could be the reason and how can I get over this issue? Any ideas? Thanks. 

[James-B]

Hey ProfX,

It might be best if you post your code so that we can look at the code and see what's going on.  It would be even better if you had a chopped down version that reproduced what you're seeing.

Also, if you could give some details of exactly what you see when it doesn't work, that would be great!