Hi E.Greene,
on FPGA I use a simple counter to generate PWM output signals:
count++
out := (count >= duty)
IF count >= fullperiod THEN
count := 0
ENDIF
All values (count, duty, fullperiod) are in ticks (or iteration time of the loop).
To have a second output with a given phase shift you just need to use the very same "count" with an offset. With my example calculation above that offset would be 167 for a loop running at 40MHz…
Best regards,
GerdW
using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019