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Maximum data rate RT host can handle (sbRIO 9602)

Hi all, i got a sbRIO 9602,

 

in my application FPGA reads data from custom module @ 1Mhz, just i'm wondering if 

RT host has the capability to read data and visualize it on a graph without losing samples.

 

I just want to know this before look how to implement any Bufferized/Producer consumer/DMA transfer 'cause

if RT host can't simply manage this data rate i will have soon or later buffer overflow.

 

Until now what i've thought is to copy 1000 contiguous samples in a memory in a ONE SHOT way, reading this memory from RT Host and visualize it on a waveform Graph.

 

But again if there is the possibility to show acquired data continuously is obviously better.

 

Thanks in advance.

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Hi Mariano,

 

with RT target you can achieve 1 kHz data transfer rate. If you have an FPGA VI that samples at 1 MHz, you need to implement a buffered transfer to RT Host.

 

So what you thought to implement is correct. You need to "package" 1000 sample and transfer "chunk" of samples to RT host.

 

Hope that this will help you.

 

Best Regards.

 

CLA_CUP

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Hi Mariano,

 


i'm wondering if RT host has the capability to read data and visualize it on a graph without losing samples.


 

- (Small) RT targets usually don't have an UI.So to show data on a graph on screen you probably need another connection from the RT to a PC which will introduce additional overhead to your target.

- Showing 1MS/s on a graph is usually overkill, you can't interpret data that fast... Think about that!

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Hi, thank you all for your suggestions.

In my RT Host i read 10000 values in every cycle so data rate drops to 1Mhz/10000 ->100Hz i think.

 

What i want to do know is to detect peaks in my data and create an histogram of that peaks in RT.

I've placed a peak detector VI that takes as input my array of 10000 values and generate an array with only peaks but i don't understand how to use Histogram PtByPt VI. It works with single data value at a time so to generate a consistent histogram i should wait 10000 cycles and so it may not  be as fast as 100Hz .

 

Previuously i've tried to detect peaks and generate Histogram directly on FPGA to be sure to be as fast as possible due to 1Mhz data acquiring, but now with 10000 values chunk i guess if i can realize this on RT host side .

 

Any suggestion will be really appreciated.

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Hi Cla_cup, sorry i've noticed now you're answer, 

how can i pack data on FPGA side to let RT host read data continuously avoiding buffer overflow?

Is there some example about packing data?

 

Thanks

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Hi Mariano,

 

I found two examples of data communication. The first one shows you how to transfer multiple channels of data through one DMA FIFO on FPGA.

 

The second one allows you to implement a lossless data transfer.

 

I hope that they'll help you.


Best regards.

 

Cla_CUP

NI Italy

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Hi i have seen.

 

My situation is this: i have 24bit FXP data read @ 1Mhz on the FPGA side

 

is possible to bitpack this data?

 

24bit data @ 1 Mhz is 3Million byte/s

 

how much deep RT FIFO side can be? how many elements per cycle can be read?

 

i haven't understood well how DMA fifo transfer works between FPGA and RT host, ie placing a waveform graph on RT host VI to show data slow down the game and involves also PC data transfer so must be for this reason that i get always buffer overflow already @500Khz ?

 

Is there a producer consumer architecture that can i use to overcome this problem?

 

 

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