Labview fpga vi and host vi give different results

[chiks]

I have made an FPGA VI that implements a compression algorithm. I have put whole of the code in FPGA VI, because I want to run it on FPGA of Compact RIO.I have put only input controls and output indicators in Host VI. Host VI doesn't do any processing part. It only takes inputs and displays outputs. But my FPGA VI front panel and Host VI front panel show different results. FPGA VI gives correct result every time. But Host VI doesn't work properly. What could be the problems ? Please help me to find the solution.  

[nathand]

Can you upload your code? Can you be more specific than "doesn't work properly"? Do you get any errors? How are you sharing data between the FPGA and host - DMA FIFOs, or front-panel controls?

[chiks]

I am sharing data between FPGA VI and Host VI by using controls and indicators. I am not using DMA FIFO. Host VI doesn't give errors. It shows wrong results.

[NukeB]

If you are just monitoring the front panel, chances are you missing data points. You didn't mention this explicitly, but it sounds like you are using Read/Write Controls.  If this is the case, those are only updated once per call, so if your algorithm is running and completes in 100 uS, you would have to update your host every 100uS (which frankly, just isn't going to happen if you are running on Windows).  Do you have an idea of how fast this is entire algorithm is running at?  Also, why aren't you using DMA FIFOs?  For a processing algorithm you have to pass back to the host without missing data points, DMA is the CORRECT option.

Can you shed any more light on what is going on in your code?

[chiks]

OK. I will try again and call you back if problem couln't be solved.

Thank You.