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Labview 2015 (FPGA) Compilation is not successful (Labview 2010 to 2015 Conversion)

Look here:

 

Support for Microsoft Windows 10 - National Instruments
http://www.ni.com/white-paper/52818/en/

 

--> "The Xilinx tools used by the FPGA Module do not officially support Windows 10."

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Message 11 of 19
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Well, I'm very surprised that the cloud compilation doesn't work. Since your screenshot implies that it is stuck doing coregen for some Xilinx IP, it sounds like regenerating that may help. From your project explorer window, go to Tools->FPGA Module->Regenerate IP Integration Node Support Files. This may or may not work on Windows10, I'm not sure. Another thing you could try is forcing LabVIEW to recompile the VI heirarchy. To do this, open your top-level LV FPGA design, and hold down [ctrl] + [shift] while pressing the run arrow. Kick off a cloud compilation after that.

 

If you're able to share your code, I'd be willing to set up a Windows 10 virtual machine to try reproducing this.

Cheers!

TJ G
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Message 12 of 19
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Amazing T-REX$,

 

It 's working. I did the "Regenerate IP Integration Node Support Files" and selected the my FPGA VI and click on regenerate. There was a message saying that there are no IP integration node found. But after that I run my VI , then boooom...It 's working.

 

I cant still understand how it happens. It is better if you can explain what is going on only for the educational purposes.

 

But anyway thank you very much for the tipp. I could save lot of time.

 

Cheers!!!

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Message 13 of 19
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This is gonna get weird.

 

I could successfully compile two times with this regenerate method. Then I did some small changes to the program (Add two indicators and changed the represenatation of a control). Get the same problem again. The progress bar stops at Generate Xilinx IP and doesnt move anymore.

 

 

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Message 14 of 19
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Farb,

 

Would you be able to attach the project that you are having issues compiling? If you are not comfortable doing that, could you upload a similar application that still shows this behavior?

 

If we are able to take a look at your project and recreate the behavior you are seeing it might be easier to spot what is going wrong.

Matt J | National Instruments | CLA
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Message 15 of 19
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Dear Jacobson,

 

Thank you for your kind response. Legally I m not allowed to publich anything also there is no other similar program. (If so I could finish the research project as soon as possible). I m pretty much sure that it is not with porgram but with the Labview 2015 compatibility because now when I m regenerating IP node files sometime prompts a Labview Clash report and suddenly close the Labview. I think NI gonna get this clash report automatically. What I can do is that posting the Xilinix log.

 

Cheers!!!

 

 

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Message 16 of 19
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Hey Farb16, was there any error code when LV crashed?

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Message 17 of 19
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I cant remember exactly. It was sudden crash and asking me to permission to send the report to NI. Anyway the problem continues with windows 10 and Labview 2015 and I switched to Windows XP and Labview 2010 again, now everything is going smoothly. I could compile my program again.
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Message 18 of 19
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Hello Folks,

I see that this thread has been inactive for a few months and was wondering if a solution was found. I have a similar problem, except I've upgraded from LV 2012 to LV 2015. I can compile an FPGA vi on the 2012 machine in about 2.5 hours (it's a big design), but I can't get the 2015 machine to compile - it gets hung at Translate. I've waited up to 17 hours (overnight run), but no results. I'm now trying the Cloud Compiler service to see if the problem continues in that environment (over 1 hour so far, still in Synthesizing). In any case, The two setups are as follows:

 

System #1

NI PXIe-1082 Chassis

NI PXIe-8133 Controller (4GB Ram)

NI PXI-7852R

Windows 7

LV 2012, FPGA Module

 

System #2

Dell M6800 Workstation (16GB Ram)

Windows 7

LV 2015, FPGA Module

 

I'm trying to compile to a PXI-7852R target in System #2 where the compiler gets hung in "Translating." I've zipped and attached the files if you want to have some fun (Single Shift Register - FPGA.vi is the top level file).

 

Any suggestions?

 

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Message 19 of 19
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