Labview 2014 FPGA memory properties change

[christian_w]

The property 'Cycles of read latency' is new in the FPGA module of LabVIEW2014 and it's default value is 1.

My LabVIEW2013 project was migrated to this setting and there are side effects because the icon is expanded by a side icon that reflects this setting by a multiplier (x1). All VI's are getting move changes and my diagrams are getting overlapping items.

Is that an intentional change? Why is the zero option grayed out?

[Intaris]

Block RAM memory items ALWAYS have one latency.  I don't have 2014 installed but I would imagine that these settings would actually make the otherwise required shift register on the output unneccessary?

Not having 0 available is because 0 is not a valid option in combination with BRAM memory.

[christian_w]

The documentation says

Cycles of read latency—Specifies the number of cycles of latency for the Read (Memory Method) of memory items implemented using block memory. The default value is 2 cycles of latency.

So why are the LabVIEW 2013 project settings migrated to 1cycle?

@Intaris

...shift registers are only required in SCTLS

[Intaris]

Do you have arbitration on or off for the block ram?  Could that explain the inherent latency?  I don't have LV 2014 installed and I only work with SCTLs so I'm actually not of much use here.....

[christian_w · Accepted solution]

In my project I use 14 memory blocks. LabVIEW 2014 migrated all of them by default to 1 cycle of latency although the documentation says the default are 2 cycles.

Beside the block diagram changes caused by the new object size, that setting leads to an FPGA compiler error.

This error can be a compilation error as shown or simply an infinite wait at phase 4.1.2. Update Timing...

LabVIEW2014 Help

Cycles of read latency—Specifies the number of cycles of latency for the Read (Memory Method) of memory items implemented using block memory. The default value is 2 cycles of latency. ...

Note  When you use the Read (Memory Method) within the single-cycle Timed Loop for a memory item implemented using block memory, the number of Feedback Nodes or uninitialized shift registers wired to the data output must be greater than or equal to the number of Cycles of read latency. If you do not wire enough Feedback Nodes or uninitialized shift registers after the Read (Memory Method), the FPGA VI fails to compile and LabVIEW returns an error.

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I had to change each block memory property to 2 cycles of latency to get a successfull FPGA compile build, although I don't use the Read memory method within SCTL's.