LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)

[Dragis]

And similar to what you did before, I would do 3-4 compiles each and then just report the averages; Xilinx can jump around a lot.

[crossrulz]

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michaeljoseph wrote:

In my actual design the FPGA usage is more extensive than the example. I've copied the resource usage summary for the latest version of my FPGA VI (several compiles of the same VI). I have the most resource intensive parts of the design completed, but I still need to add some more things (hopefully they will fit).

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If you are getting that full with still more to be added, I recommend giving your local NI representative a call and see if they can hook you up with an NI Systems Engineer.  Those guys are really good and will likely be able to find some good tweaks and/or redesigns to get that usage down.