LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred

[WillsG]

Hi,

I am trying to build a LabView FPGA VI. During compilation, I always get error stating "LabVIEW FPGA:  An internal software error in the LabVIEW FPGA Module has occurred.  Please contact National Instruments technical support at ni.com/support".  At the time, comiplation process is almost at the end.  "Final Timing (place and route)" shows as completed. When Checked the Xilinx log session, at the end it states that "  Process "Generate Programming File" completed successfully". However, I do not see any generated bitfile.

When clicked on error details, it shows following: 

LabVIEW: An unknown error occurred.

Error -2629 occurred at Error occurred while loading XML string. Invoke Node in niFpgaXml_PrettyPrint.vi->niFpgaWriteBitfileXml_Core.vi->niFpgaCompileWorker_CreateBitfile.vi->niFpgaCompileWorker_JobComplete.vi->niFpgaCompile_Worker.vi:6460001

Possible reason(s):

LabVIEW: An unknown error occurred.

I tried multiple times but so far no luck to generate bitfile for this VI.  What could be wrong here?

I am using Labview 2013

[Intaris]

Chekc that you're not trying to replace a bitfile which is either write protected or you simply don't have the rights to create a new file in that directory.

IIRC the old bitfile is deleted relatively early int he compilation process but the generation of a new bitfile is attempted only after the full compilation has completed.  Anything which will prevent you from creating this file will possibly lead tot his error.

I'm pretty sure I ran into this problem before and I solved it by changing the permissions on the folder I was trying to create the new bitfile in.

[WillsG]

Thank you, Intaris for your imput.

I made sure that Bitfile directory has write/modify permission but my problem still persist. I created a small footprint VI just to check the compilation success and that seemed to work okay.

Sometime (rarely) I alo get an error message stating:  "Memory is Full".  Following is snapshot of that error. This happens occasionaly. However, 1st error is persistant on every compilation. Not sure is those are related.

[PeanutButterOven]

What percentage of the FPGA resources does your code use?

Mark B.

[WillsG]

Hi Mark,

Here is the device utilization Summary. My development system is running with Windows-7 (32 bit) with 3GB RAM and Labview 2013. 

Device Utilization
---------------------------
Total Slices: 90.0% (11970 out of 13300)
Slice Registers: 40.7% (43258 out of 106400)
Slice LUTs: 71.6% (38103 out of 53200)
DSP48s: 1.4% (3 out of 220)
Block RAMs: 22.1% (31 out of 140)

Timing
---------------------------
40 MHz Onboard Clock
: 40.00 MHz (57.90 MHz maximum)
80MHz (Used by non-diagram components)
: 80.00 MHz (100.19 MHz maximum)

--WillsG

[PeanutButterOven]

WillisG,

The first error you are seeing is related to memory usage on the CPU (as is the second error). It is possible that the 3GB of RAM is not enough to run everything in your system (not sure what else is going on in the background while you are compiling). I would suggest trying to compile any of our FPGA shipping example projects to see if it is possible. Also you may want to minimize all other CPU tasks/process while compiling your code.

Mark B.