Justification of Hardware in HDL Synthesis Report in Xilinx Log File generated by LabVIEW FPGA

[ewaqas]

Hello,

I have a question i want to check in LabVIEW FPGA that if i am using only 17 bit adder(High Throughput Maths) on block diagram in LabVIEW FPGA and compile this code after compilation in xilinx log file in HDL Synthesis Report it shows following:

HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 12
11-bit adder : 1
13-bit adder : 1
14-bit adder : 1
14-bit subtractor : 1
17-bit adder : 1
2-bit subtractor : 2
25-bit adder : 1
26-bit adder : 1
3-bit adder : 1
4-bit subtractor : 1
8-bit subtractor : 1
# Registers : 232
1-bit register : 170
11-bit register : 1
13-bit register : 1
14-bit register : 2
17-bit register : 2
2-bit register : 36
25-bit register : 1
26-bit register : 1
28-bit register : 1
3-bit register : 1
32-bit register : 10
4-bit register : 2
64-bit register : 1
8-bit register : 2
96-bit register : 1
# Comparators : 2
10-bit comparator greater : 1
17-bit comparator greater : 1
# Multiplexers : 171
1-bit 2-to-1 multiplexer : 138
1-bit 3-to-1 multiplexer : 2
1-bit 6-to-1 multiplexer : 3
14-bit 2-to-1 multiplexer : 1
17-bit 2-to-1 multiplexer : 2
3-bit 2-to-1 multiplexer : 4
32-bit 2-to-1 multiplexer : 16
4-bit 2-to-1 multiplexer : 1
64-bit 3-to-1 multiplexer : 1
8-bit 2-to-1 multiplexer : 2
96-bit 2-to-1 multiplexer : 1
# Decoders : 1
1-of-32 decoder : 1
# Tristates : 63
1-bit tristate buffer : 63
# FSMs : 6
# Xors : 12
1-bit xor2 : 12 

How can i justify this above resource while i am using only one adder in my code ?

Any one can justify this please?

Xilinx Log File and fgpa vi compiled is attached !

***Actually i have another code i compiled and saw some resources which am not using in my coding so for testing i use a simple vi with add function to check resources

Also if any one can explain exact No of hardware resource for below functions?Am asking this because i know the basic idea but in log file it shows more resources than my expectations.

1- Adder

2-Subtractor

3- Multiplier

4-index Array

5-Round to nearest

6-Select Statement

7-Loop Counter

8-less than

9-Greater Than Equals

10-Equal

11-Integer to Binary Array

Help in this question is highly appreciated

Thank You  

[nathand]

There's some overhead in FPGA resources for the communication between the FPGA and the front panel; I haven't seen that quantified anywhere, but that's what you're seeing. For example, you need some registers to store the 0 and 1 constants, and more to store the results of the computation and make it available on the front panel.

NI used to have an FPGA Resource Utilization table that showed how many flip-flops and lookup-tables are used by most functions, but that seems to have vanished from the web site, and in any case it hadn't been updated in years so at best it would have been an estimate.

Do you really need to know how resources are used at a low level? If so, why are you coding in LabVIEW? 😉

[ewaqas]

Nathand Thank You for the reply,

Yes i Know LabView FPGA uses registers to store value from Front panel but my main concern is that if am using one 17 bit adder then why report is showing more than one adder my main concern is on arithmatic operations and MUXs.

And i am not using only LabVIEW FPGA i have an ASIP code on Vivado Suite and NISC Code in LV FPGA, So after compilation i have to build hardware schematic for both ASIP and NISC and build a resource, Area, Timing comparison.This kind of work am trying to do.

If am seeing these additional resources how can i justify and show them in hardware schematic?

there are two titles in Xilinx Report

1- HDL Synthesis Report

2- Advanced HDL Synthesis Report

Resouces shown in both differs. Why ?

Thank You 

Regards

Waqas

[Reyquaza]

Hi Waqas,

This board is better suited to LabVIEW programming questions and general compilation errors. For detailed questions about how the Xilinx compiler assigns code to FPGA resources, you may be better off posting on the Xilinx forums here: https://forums.xilinx.com/

[ewaqas]

But i am using labview fpga then why i post my problem in xilinx forum?

[Reyquaza]

NI FPGA Hardware uses Xilinx FPGA chips; you can refer to this article for more information: http://digital.ni.com/public.nsf/allkb/ED6FC9CF7B983CFD86256DCE0072E313. The compile tools used are also associated with Xilinx. For this reason, I thought it might be helpful for you to visit the Xilinx forums, as they might have more insight into how the compiler allocates specific resources.

What I can tell you is the same thing nathand said: there's overhead in FPGA resources for several things. Error handling, front panel communication, and communication with the RTOS are all implemented in FPGA resources, and are likely causing the extra resource utilization you're seeing.

[Nan.Yang]

>> How can i justify this above resource while i am using only one adder in my code ?

>> Any one can justify this please?

As nathand and Reyquaza mentioned, these resources you are seeing is the overhead of LabVIEW FPGA design. LabVIEW FPGA does a lot work behind the scene so that your FPGA VI can communicate with your other VI on RT and PC without requiring you to write any communication code. It also allows you to run your FPGA VI in interactive mode, so you can change the values in controls in the front panel, and see the results in indicators while the FPGA is running. It also handles synchronization to I/O pins, and so on.

You can compile an empty VI in LabVIEW FPGA to see how many resources are used for above purposes. Usually this only takes a small amount of your FPGA resources and you don’t need to worry about it. If you want to know how many resources are used by your code, you can subtract resource utilization of your VI by the resource utilization of an empty VI, to see the actual numbers. Of course you need to compile both VI on the same FPGA target.

Please be noted that the resource utilization in Synthesize report only shows the “logical primitives” to implement your design. It does not include everything on the FPGA, nor is it accurate to represent the actual resource usage. These will be mapped to LUT, FF, DSP48 and Bram during Map step (or Place step if you use Vivado compilation tool). It is the hardware resources, in terms of LUT, FF, DSP48, Bram, that determines whether you design can fit to a particular FPGA device. You can find the numbers on Final Device Utilization report in LabVIEW FPGA when the compilation is complete.

For your code in Capture_Adder.GIF, I see you connected a constant 1 and constant 0 to the High Throughput Add node. In this case, actually the adder will be optimized out by LabVIEW FPGA because it knows the result is constant 1. So this code only requires a few registers to store the number 1 in x+y indicator.

>> Also if any one can explain exact No of hardware resource for below functions?Am asking this because i know the basic idea but in log file it shows more resources than my expectations.

The exact number of resources depends on a lot of factors, namely whether the compiler can do optimization on the code, whether these functions appear inside Single Cycle Timed-Loop (SCTL) or outside SCTL, whether it requires additional optimization for timing closure, etc. And when your code becomes complex, the compiler always find ways to optimize the code and reduce resource utilization. So I would suggest to not worry about the resource utilization, unless resource is the bottleneck of your FPGA design. I can give some general ideas though. I assume you refer to integer and/or fixed-point operators, not floating-point operators.

>> 1- Adder

>> 2-Subtractor

They take very little LUTs and FFs (Registers), proportional to the bit width. It may take extra resources if you select different rounding modes and saturation modes.

>> 3- Multiplier

It takes logic resources as well as DSP48 resources. This sometimes becomes the bottleneck of your design. Carefully design the bit width and pipeline stages of your multiplier to get best timing and resource utilization.

>> 4-index Array

Takes very little resource to handle index out of range cases.

>> 5-Round to nearest

Equivalent to a comparison plus a select.

>> 6-Select Statement

Equal to a mux.

>> 7-Loop Counter

It controls node execution order inside a loop. It takes very little resources, comparing to the nodes that may appear in the loop.

>> 8-less than

>> 9-Greater Than Equals

>> 10-Equal

Take roughly same resources as a Subtractor.

>> 11-Integer to Binary Array

Take nothing in hardware.