Is it possible to write the same FIFO within a SCTL and outside?

[B.Buerkert]

Hello,

can anybody tell me if its possible to write into the same FIFO inside and outside of a sctl?

The Sctl runs an write data into the fifo till an external event stops the sctl.

Than i want to write some values in the same fifo, that makes sure that the data is on the position where the external trigger stopped the sctl.

After that is written, the sctl starts running again.... and so on.

Possible or not? Because i allways get an error from the compilier.

Thank you.

Greetings,

B.Buerkert

[crossrulz]

The SCTL is what is limiting you.  The SCTL needs exlusive rights to writing that FIFO or else it won't be able to run in a single cycle.

[crossrulz]

After thinking about this for a little bit, you may be able to turn off the Arbitration and get this to work.  Go into the dialog where you setup the FIFO.  Go to Interfaces.  For the write, configure it to Never Aribitrate.

[B.Buerkert]

Hy,

i changed the arbitration to never, but i still get an error:

resource interfaces requestet from both inside and ouside the sctl...

Any other ideas? 😕

[nathand]

Is this a DMA FIFO, or is the FIFO internal to the FPGA? Sounds like you may need to restructure your code.

[B.Buerkert]

Hy,

it a targed scoped fifo 🙂