Is an FPGA Host Interface a blocking shared resource?

[Southern_Cross]

I'm curious to know if the FPGA Host Interface node is a shared resource. Meaning, if I have a Timed Loop on a LabVIEW Real-Time target (e.g. cRIO) that is reading and writing from the FPGA using the Host Interface. Will the determinism of that loop be adversley affected if I access other signls on the FPGA using the Host Interface in a separate loop (either a Timed loop or a normal while loop).

Said more tersely, is the FPGA Host Interface a shared resource that can cause a priority inversion if called from two seperate loops?

Thanks.

[WenR]

Hi Southern_Cross

According to our documentation, you should be able to have more than one reference to the FPGA open at the same time ( as long as all the references access the same VI in the FPGA), and use them all in different places in your code from the same target. Since you can only have 1 main VI in the FPGA, accessing the reference of the FPGA behaves more like an I/O than like a non reentrant VI. 

Using Multiple FPGA VI References for the Same Target (FPGA Interface)   

As long as you are not writing the same variables in both loops (which could cause a race condition) you should be fine.

WenR

[speleato · Accepted solution]

Hey Southern_Cross,

The Host Interface as a whole is not a shared resource that's protected by a global lock, but calls to specific host interface functions may acquire locks to protect shared resources. If you let me know what you are calling from each loop, I can let you know what sort of interactions are possible.

Priority inversion should not occur. Are you seeing something that looks like priority inversion to you? If so, I'd be interested in the details, as that's the kind of issue we take seriously.

Thanks,

Sebastian

[speleato]

---

 As long as you are not writing the same variables in both loops (which could cause a race condition) you should be fine. 

---

By variables, do you mean a front panel control? By design, it is safe to access the same controls and indicators from multiple threads. Are you aware of specific cases where that is not the case?

[Sam_Sharp]

I think the only one that I've encountered that's blocking I think are the FIFO functions.

[Southern_Cross]

Thanks all. This was helpful.

This question came as I was preparing to do some changes to my approach that would involve multiple Timed Loops reading from the same FPGA VI (but different controls and indicators). Before sinking time into prototyping this I turned to the forums/docs and didn't see the answer so I thought I'd ask. Turns out the answer was in the link WenR posted but I had missed it in my searches: http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgahosthelp/multiple_fpga_refs/

Thanks.