Incremental FPGA builds?

[ToeCutter]

I was talking to a colleague yesterday and he was discussing the ability to incrementally build FPGA code, so he could instruct the compiler not to rebuild specific parts of his FPGA design that were locked down. This kind of thing sounds like it could save us a lot of compile time and effort.

1) Is there anything like this possible in LV? (I haven't seen it)

2) Has there been any discussion of these features? If not, I'm toying with the idea of raising it on the idea exchange.

[thoult]

This might be of interest.

It covers the points that I'd considered regarding utilisation/optimisation. Sadly, there's no discussion.

Perhaps time for a revisit / meatier idea?

[ToeCutter]

Thanks for the link, thoult.

I think it is time for a revisit. I will wait for a few more comments first. Maybe some LabVIEW R&D may swing by this thread and add their 2 cents?

In the meantime, let's Kudo the idea you linked.

[crossrulz]

Diagram Disable Structure...Nevermind, misunderstood the idea.

There are some really neat tools that were new with 2013 where you can emulate inputs and outputs to test your FPGA code.  I haven't had the chance to play with these, but they were discussed at the NI Developer Education Day.  Those might be an alternative for most situations.

[Intaris]

I believe this is called "partitioning" and it usually goes hand-in-hand with some degree of manual placing of the functionality on the chip in question.  Since NI does not offer any such abilities for LV FPGA code, I doubt it'll be supported in LabVIEW any time soon.

This is usually utilised in conjunction with code which has defined hardware requirements (such as a filter bank which utilised many DSPs) and the ability to optimise the module in itself is desireable.  I'm not sure how the xilinx compiler goes about optimisation in these cases.  It could also be that you're artificially limiting your optimisation possibilities due to the declaration of unmovable blocks of code.

HERE.

Shane.