How to use buffered digital change detection? Time interval between earliest and latest signal change is <100ns

[ossoo]

Hi,

I use PCI-6229.

My Problem is:

use 4 digital channel input channel to aquire signals B, C, D, E and 1 dgital signal to generate signal A.

After I sendout a digital signal A, signal B, C, D, E response should response almost at the same time - Time interval between earliest and latest signal change is <100ns. 

I need to check whether these 4 channel response at the same time. So I want to use Digital Change Detection as the file attached. But the processing time for each value change is too slow.

Is there anyway fast enough to catch the real digital change?

Thanks

[The_Red_Barron]

Howdy ossoo!

The maximum clock rate for digital I/O with the PCI-6229 is 1MHz (sampling every 1us).  Unfortunately, this will not be fast enough to detect the event in your system which is less the 100ns in duration.

Consider using a High-Speed Digital I/O  device or a High-Speed Digitizer  for your application.

Regards,

[ossoo]

The Red Barron,

Thanks for your information.

I saw the function Change Dection in LabView. It use a 80M Hz clock to detect the digital change. Maybe it works?

Also, although the maximum clock rate for digital I/O with the PCI-6229 is 1MHz, but in may programming, sometimes it only allow me to use max 100K clock rate. I don't know what's the problem??

[The_Red_Barron]

Change detection will let you know that a digital change has occurred, but it will not give you the timing information you want.  Even if you are sampling at 80MHz it will not be fast enough to detect events with 100ns resolution.

The PCI-6229 uses correlated digital I/O which means the DIO engine does not have its own clock source and must use the clock from somewhere else.  That clock can be up to 1MHz and come from any PFI, RTSI, AI Sample or Convert Clock, AO Sample Clock, and Ctr n Internal Output.  If the source you have chosen to use for the correlated clock is only 100K then you should not be able to specify a clock rate greater than that.

Regards,

[ossoo]

The Red Barron,

I am confused about the digital clock and Change Detevtion timebase. Like the example below:

I have a digital pulse with pulse width 100ns. I want to get the number how may digital change occure. I connect the signal to a DIO channel and use Change Detection to measure. The result will be 1 or 2?

If it is 2, does it mean the clock for this DIO change to 80MHz automatically in case I use Change Detection. And the clock rate limite 1MHz won't be a problem.

If I want to get the timing information, I use counter Count Edges to syncronize. Can I also get the right timing information?

Thanks

[The_Red_Barron]

Using the Change Detection form of the DAQmx Timing VI as you did in your example means that when a change occurs it will sample the value on the digital input line.  This effectively makes the signal on which you are detecting changes act as the digital input clock.  When you have the same channel set for the rising edge and falling edge of the Change Detecting VI then the digital input will be sampled on both of those edges.  NOTE: The DIO lines can operate at 1MHz so if the signal on which you are detecting changes is switching faster than that you will run into problems.

If you are just trying to count the number of times a signal changes then you should simply use a Counter Input task to Count Edges.

Regards,

[John_P1]

Hi ossoo,

Change detection is the way you would have to do this on a 6229.  With change detection timing, the external signals can be used to sample the DI lines on a rising edge, falling edge, or both.  In your case you probably are only interested in rising edges.

When one of the specified lines changes, the board generates an internal signal called the Change Detection Event.  You could use this signal to sample the 80 MHz timebase with a counter in order to provide a timestamp of when the change occurs. 

The basic configuration would be:

1.  Configure DI Task with Change Detection Timing

2.  Configure a Counter Input Edge Count task.  The source of ticks would be the 80 MHz timebase.  Set the task to use a sample clock, with the source being the Change Detection Event.  Configure an Arm Start Trigger if you want to have a deterministic start time (I would suggest to use your output pulse).

The result of reading the data back from these two tasks would be an array of digital data and an array of timestamps from your counter, telling you when the signals were picked up by the change detection circuitry.

One caveat is that the maximum spec'ed sample rate for a DI task on the 6229 is 1 MHz.  If you have multiple changes occurring much faster than this, eventually you might get an error stating that the device could not push the samples into the on-board FIFO quickly enough.  This may or may not be an issue for you, but I think the above suggestion is certainly worth a try.

If the above idea does not work, I would recommend that you consider an X Series board for this task (e.g. PCIe-6320) assuming you only need to timestamp 4 signals.  You could synchronize the 4 counters with the output of signal A (on a DO line), then measure the timestamp of the 4 return signals with a 10 ns resolution (100 MHz timebase).

Best Regards,