LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

How to stop FPGA VI on EtherCAT (NI 9144) FPGA?

Solved!
Go to solution

How to stop FPGA VI on EtherCAT (NI 9144) FPGA?

 

I have a FPGA VI run successfully on NI 9144. However as the block diagram of the VI is inactive, I cannot stop the loop.

I have tried to open a FPGA vi reference and use invoke method to abort the VI or other FPGA interface functions but they are not supported on EtherCAT FPGA.

I then created a user-defined variable, to send stop command from RT to NI 9144 FPGA, but it did not work either.

 

Dose anyone know how to stop FPGA VI running on EtherCAT (NI 9144) FPGA?

Thanks

0 Kudos
Message 1 of 5
(3,236 Views)

you should be able to use a user defined variable to stop it, I have done it before. One possible way that is fairly foolproof is to use a simple integer UDV. Have a loop in the cRIO fpga looking at it in a loop. If the value changes, then the etherCAT fpga stops.

0 Kudos
Message 2 of 5
(3,176 Views)

@MarkCG wrote:

you should be able to use a user defined variable to stop it, I have done it before. One possible way that is fairly foolproof is to use a simple integer UDV. Have a loop in the cRIO fpga looking at it in a loop. If the value changes, then the etherCAT fpga stops.


Thanks very much for your replay. I used a boolean UDV, but it didn't work. Is it the problem? Any thought?

0 Kudos
Message 3 of 5
(3,172 Views)
Solution
Accepted by topic author Noriker

I think becasue it runs the variable engine code in the backround you cannot stop the frame loop and leave the FPGA in an idle state. I would recommend to use nested while loops where you have a while loop always running and start and stop another loop inside.

Message 4 of 5
(3,169 Views)

@DirkW wrote:

I think becasue it runs the variable engine code in the backround you cannot stop the frame loop and leave the FPGA in an idle state. I would recommend to use nested while loops where you have a while loop always running and start and stop another loop inside.


Hello, thanks for the reply. Now I have better understanding of FPGA which is not designed to stop. Thanks very much again.

0 Kudos
Message 5 of 5
(3,143 Views)