How to set FIFO depth and number of elements in DMA FIFO host side

[tintin_99]

Hi ,

I have a DMA Fifo on the host side that read the elements from the target DMA.

In my host side I contiously call a function at a specific rate and each time I call it I collect I collect 48 elements.

So for example the rate that I call this function is 1kHz and I have to call this function 96000 times ( 2s of data ) and in each call I collect 48 elements.

I used FIFO Read in a loop to make sure the FIFO doesn't overflow. As can be seen below I first set the FIFO depth then I read the elements in a whiel loop but how can I set these numbers. Using these number the final number of elemets in the FIFO is zero but how about if I want to call this function in the FPGA at rate of 10kHz and I may call it 5000000 times . Then how should I set the FIFO

Thanks 

[nathand]

I'm trying to understand your question. Your image shows that you're reading 24000 elements at once but your text says you're collecting 48 elements at a time. What's actually going on here? It might help to show more of your VI.

What happens to the data after you read it from the FIFO? Normally you would pull data off the FIFO continuously, so the buffer size isn't that important so long as it's large enough.