How to route signals in LV FPGA?

[mtzhang]

In my LV FPGA, I have one signal in named Clk_a from pin1, now I just want to route this signal to another pin2, just like "assign clkb = clka;"  in verilog design, so how can I route signals from different FPGA IO Node?

[GerdW]

Hi mtzhang,

I have one signal in named Clk_a from pin1, now I just want to route this signal to another pin2

Place an IO node for pin1 and for pin2. Use a wire to connect them…

[mtzhang]

but this will run only once

if I put this in SCTL, the signal change can only be detected on the rising edge of the sysclk

what I want to do is just "assign clka = clkb",like in verilog module ,not by any clk

[GerdW]

Hi mtzhang,

I did some amount of FPGA programming, but never digged that deep into the hardware.

Maybe you should ask NI directly!? (Do you have an active SSP?)