How to reduce the time of compiling in FPGA?

[yuefeiw]

I wrote  some code for PID control by using FPGA .But only if a little change is in the code,i have to recompile the code .It takes about 15 minutes per time. It is time-consuming and terrible.

Could anyone have the good way to fix the problem?

Thanks

[Dragis]

Unfortunately, when you compile for the actual hardware, you are generating a custom application for an entire FPGA which takes time. To reduce the design cycle, use the development features for executing your code on the desktop to quickly find functional issues. After that, you can simulate the code with Xilinx ISIM or Mentors ModelSim to find cycle-level timing issues. At that point, the code should be ready for deployment and hopefully will work on the first compile for hardware.