How to obtain negative phase difference (signal 2 does not appears)?

[mathijsen]

Hi! There is a vi to calculate phase difference of waveforms acquired via FPGA. But I found one problem. For example - in real situation if firstly should appears signal 2 (wave 2) - Phase Differerence should be negative. But this vi does not even show red wave 2 on chart if I put manually phase offset negative Expected Phase difference - works properly and shows negative value, but Calculated Phase Difference in this case - 0, and it is wrong (on PrintScreen.png). How to obtain red wave 2 on graph and negative calculated phase difference? Thank You in advance. 

[mathijsen]

I think that the problem in unsigned integers - negative values are lost. But even if I changed WaveformFIFO -Properties-Data Type to "Signed FXP" and change values from I16 to FXP in GenerateSignal(FPGA).vi file, but it is not solved the situation. Where can be problem else?

[GerdW]

Hi mathijsen,

there is no timing in your FPGA VI, so the FPGA will fill the FIFO as fast as it can (40MHz loop?)!

In your host VI you don't provide any timing when creating the waveforms.

You should separate your two problems here: waveform generation including transport of data to the host vs. all math done with your waveforms.

You can check your math easily when using some signal generation functions instead of your FPGA.

And you can check your FIFO data using some probes/indicators…

[mathijsen]

GerdW,

Thank You for advice. The problem which I can`t still avoid that when I changed in GenerateSignals.vi in Phase Offset properties from unsigned FXP (range from 0 to 1) to signed FXP (range from -0,5 to 0,5) - appears red dot on Sine Wave Generator. It is still impossible to obtain negative Phase Offset. What can I change to solve it?

[jozef.liptak]

Hello,

the value you wire to this terminal must be an unsigned fixed-point data type with a 32-bit word length and a 0-bit integer word length. You have changed to signed integer, therefore the red coercion dot. Those functions dont allow negative input (refer to LV Help for this function). If you need negative delay, just delay the other generator (or switch the inputs to the Build array in the GenerateSignals(FPGA).vi), and it will appear as the other signal is delayed... Those things are relative. 

Still you will never get negative reading on the output of the Phase difference 2010.vi. It is programed so, that it returns absolute phase difference (review the code). You need a different approach to this... And remember, that 90° is the same as -270° and so on...

B/R