01-19-2016 07:54 AM
hey,
I am using CRIO FPGA for detection of input digital signal. I have found an example named Hardware Trigger Detection. As it implies, I replaced controls with an FPGA IO module (I have attached the file). However, It takes a long time to compile and it seems stuck at "generationg core" for ever.
Can any body give some suggestions? Thank you!
01-19-2016 08:00 AM - edited 01-19-2016 08:00 AM
Hi oilpig,
what's the purpose of the upper sequence?
Are you sure about implementing the THINK DATAFLOW paradigm correctly?
After fixing this quite bad problem: are you sure you can read your digital input at 40MHz?
Which digital IO module do you use?
01-19-2016 08:09 AM
Hey,
Thank you for your reply! The upper sequence is implemented to detect rising edge of IO16.
I am sorry. What do you mean by THINK DATAFLOW?
I am using NI 9403 but I am not sure whether I can implement 40 MHz for this module. Can you tell me how to judge it?
Thank you!
01-19-2016 08:17 AM - edited 01-19-2016 08:17 AM
Hi oilpig,
The upper sequence is implemented to detect rising edge of IO16.
Well, it will never detect any signal edges…
What do you mean by THINK DATAFLOW?
When programming with LabVIEW you should know the term THINK DATAFLOW and it's meaning!
Did you read the LabVIEW help on that topic?
I am using NI 9403 but I am not sure whether I can implement 40 MHz for this module. Can you tell me how to judge it?
I would start by reading the manual and specifications for that module!
01-19-2016 08:35 AM
Thank you!
I think the problem should be local variable cannot update within former timed loop. So I changed it to while loop and update indicator of IO16 each iteration. Can you help me judge whether it is suitable for detecting rising edge of IO16? Because it seems that it is stuck at 'Generating core' again this time.
I will read relating material for THINK DATA FLOW and my IO module.