How to assign 2 individual thread on different core(processor) and execute both thread deterministically and continuously?

[AmitYadav]

Hi friends,

I have piece of code which does the following

Read input -> process the data -> generate output, all this is done inside a timed loop as it is a top level VI and is to be time deterministic.

This code is running on NI Real time target machine which has 2 core (above mentioned timed loop is assigned to core 1)

As the code has become heavier on 'read input' and 'generate output', I would like to

- Divide the read input function into 2 section(read input 1 & read input 2) and generate output function into 2 section(generate output 1 & generate output 2)

I want to have same functionality as earlier but run

Read input 1 and read input 2 parralely on core 1 and 2 -> then process the data -> generate output1 and generate output2 parralely on core 1 and 2

Question is

How can I specify Read input1 and Read input2 to run on different core parralely inside a timed loop ?

[AmitYadav]

Hi guys,

I have tried timed structure for both 'read input1' and 'read input2' inside a timed loop. As it helps me defining the core for both and run parallely.

But the timed structure being called in every iteration of timed loop it is taking more time than usual (may be because of timed structure overhead).

Please can any 1 suggest how to execute 2 section of code parallely and deterministically?

[crossrulz]

If you want things to run in parallel, they have to be in differenent loops.  And everything inside of a timed loop is a single thread.

What it seems to me is what you really need are seperate loops for your Read and Output.  Have a single loop that reads the data at the given rate and use an RT FIFO to send the data to another loop for processing and output.

[AmitYadav]

Hi,

If I make 'Read Input' functionality in different loop, how will ensure that :

after an iteration of 'Read Input', the data(signal read data) is succesfuly transferred to the other loop containing 'data processing' and it utilises the Read data and then generate output.

As both loop are independent in their execution.

I have a concern that all the above mentioned execution should complete in a fixed time (as per now 1ms). If I miss a data in an iteration, then after 1ms only I would be able to read the data in the other loop.

As both loop as are not sync or sequenced there are chances of missing the data in some iterations.

Could you suggest any idea how to transfer data without any miss.

[crossrulz]

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@AmitYadav wrote:

I have a concern that all the above mentioned execution should complete in a fixed time (as per now 1ms). If I miss a data in an iteration, then after 1ms only I would be able to read the data in the other loop.

As both loop as are not sync or sequenced there are chances of missing the data in some iterations.

Could you suggest any idea how to transfer data without any miss.

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RT FIFO works just like a queue.  As long as both loops are running at a set rate, you will not miss any data points.  In fact, I would probably have the outputs not even use a Timed Loop.  Just a normal While loop with no waits so that it can process the data only when there is data in the FIFO.

Of course, I do not know what all you have happening in your RT system or even which RT you are using.  So this advice is not absolute.

[Bob_Schor]

Use a Queue, as in the Producer/Consumer Design Pattern (which you can find by going File, New... (dots are important!), and finding the Producer/Consumer Design Pattern template.

In my Real-Time code, I reserve a core for the Timed Loop, which only does acquisition.  Since it is running on an RT system, I use an RT FIFO (big enough for 10 clock ticks) to export the data to a parallel (Consumer) loop.  As it turns out, I do little processing of the data on my PXI, but ship it in blocks of 50 samples (via Network Streams) to the host PC, so as soon as the FIFO is emptied, the data are put on an "ordinary" Queue for a second loop that handles sending blocks of 50 points to the PC (making this Consumer Loop for the RT FIFO also the Producer Loop for the "Send-to-PC" Network Streaming loop).

These latter data processing loops share the remaining processing power, but all run in parallel, depending on the Queues to "buffer" data.  I have put "checks" (clock and other signals) into the Data Stream (at the level of the Timed Loop) to ensure that all of the data are being send and received by the PC.  Our typical experiments last 30-60 minutes and involve transfers of 16-24 channels at 1KHz, and so far, we've not missed or lost any data ...

Bob Schor