How can I reduce FPGA compiler time

[Jasper_B]

Hi,

I am trying to implement a PID control loop on the FPGA of a cRIO. 

The VI which runs on the FPGA target takes very long to compile (1h+).

Does anyone have an idea while the compilation takes so long and how I might be able to inprove compilation time?

The program can be found in attachment.

Best regards,

Jasper

[Dragis]

That time is mostly spent calling the third party toolchains (aka Xilinx) to create the FPGA image. The only way to speed that up is to get a machine with more resources. You can purchase this machine yourself (or for your group) or you can use the Compile Cloud service which has a pool of dedicated, very fast machines specifically designed to do these compiles well. Another resource of interesting would be https://www.ni.com/en/support/documentation/supplemental/12/labview-fpga-compile-worker-compile-time....

[BFeigum]

Hi Jasper,

FPGA's normally take a very long time to compile compared to software compilations. 1 hour sounds about right for a slightly above average sized project. Compile times of anywhere from 2-4 hours (and longer for larger devices!) are not unheard of.

Companies who are serious about FPGA compilation and rely on quick turnaround invest in servers which contain many computers to work on the compilation (this is also why when you compile, it asks you if you would like to compile on the "local sever" (your computer) or an external server).

NI also has a cloud compiler available that will let you compile your code on their servers, however you must pay for the time. I think they offer a free trial if you wanted to see how it works.

So if you seriously need quick turnaround, you must consider some serious hardware.

Otherwise, you will have to queue up multiple compilations and let them run overnight like the rest of us.  

[SnowMule]

Amazon EC2 is another good resource, if you don't mind setting up the software on a machine instance (or ten).  Insanely powerful computers for cheap.