07-06-2010 01:48 PM
Hi,
I'm attempting to program a lock-in amplifier on an FPGA board in LabVIEW, but I keep receiving errors while compiling. I have a phase locked loop VI within a single cycle timed loop, and within that loop are various sub VIs with high throughput math functions. When I attempt to compile these sub VIs, I get an error saying that the high throughput functions are configured to be within a single cycle timed loop but they are not in a loop. If I switch the configuration of the high throughput functions to not within a single cycle timed loop, the error message tells me the function is within a single cycle timed loop.
Below I have attached the Costa Loop and all of its sub VIs.
Thanks,
Eric
07-07-2010 06:17 PM
Eric1493,
Thanks for the code and the detailed description of the issue you are having!
What Hardware are you using? What Software Versions of LabVIEW and LabVIEW FPGA are you using? With this information I can try to replicate the issue.
If you were to make a simple test VI that has 1 High Throughput Math Function in a Single Cycle Timed Loop, does this issue still happen?
07-08-2010 09:25 AM
Ben S,
Thanks for your reply. We already resolved the issue, however. Next time I will remember to post the hardware and software I am using.
Thanks again,
Eric
06-08-2014 06:37 AM - edited 06-08-2014 06:37 AM
Hello Eric,
I would like to use your SCTL PLL, is there any chance you can post the corrected version ?
Thanks a lot.