High Speed Streaming with Multiple FPGA FIFOs and TDMS Advanced Asynchronous (Data Ref)

[jp82]

I am using an FPGA with adapter card (7962 with 5751) for data acquisition and signal processing. I have adapted the FlexRio example "High Throughput Streaming," which works very well for a transferring data from the FPGA via a single FIFO. This example uses the TDMS Advanced Asynchronous Write (Data Ref). The "High Throughput Streaming" example is similar to "Streaming External Data to a TDMS File (Windows)" but includes more code to prep the FIFO buffer size and TDMS size.

My question is how can I adapt this code to incorporate multiple FIFOs that write data to different channels in the TDMS file? Can I use multiple instances of  TDMS Advanced Asynchronous Write (Data Ref) in a single VI for each FIFO Acquire Read Region? If so, how do I insure that the correct data is written to the correct channel in the TDMS file?

[dems]

I've never used the eDVR version, but with the advanced synchronous API, you can use this:

http://zone.ni.com/reference/en-XX/help/371361J-01/glang/tdms_set_channel_info/

Basically you call that VI <N> times with the configuration you plan on giving the TDMS file. For example, if you want to write 7 doubles that all belong to the same channel, then 8 I64s that alternate between chA and chB, you would call that function twice with these parameters:

{"non interleaved"; "Group Name", ["Ch 0"], <double>, 7}

and

{"interleaved";"Group Name", ["Ch A", "Ch B"], <I64>, 4}

All you're doing is setting metadata that the TDMS file will hold on to, and when you write to the file its going to interpret the data you send in, in that exact order, in that exact way.

[deppSu]

Bascially, the TDMS Advanced API write meta data seperately from writing raw data. You use TDMS Set Channel Information VI  for the meta data and then logging raw data with TDMS Advanced Asynchrounous Wrtie, unlike "TDMS Write" which you can set channel information as input for each write.

Thus, for your case, unfortunately, you can't use multiple "FIFO Acquire Read Region" and "TDMS Advanced Asynchronous Write (Data Ref)" to write multiple channels in one TDMS file. However, you can adapt it to write mulitple channels in multiple TDMS files. (multiple TDMS Advanced Open with TDMS Set Channel Information VIs)All this can be done in one VI. After the logging is finished, you can manually concatenate these TDMS files to one.

[DelphineL]

Hello I am interested by the issue on this question since I am exactly in the same situation.

I have adapted perfectly the program for 1 channel, but now I need to acquire several channels simultaneously.

Is it true that we cannot write several channels with the asynchronous writing?

Because then, how to be sure that the writing in different files is synchronous?

Maybe it is better to write several channels in the same fifo?

[deppSu]

Of course you can write several channels with TDMS asynchronous writing. What I mean in my last reply is that you can't bind asynchronous  write call with a channel as you do for TDMS standard write. TDMS Advanced API differs a lot in programming than TDMS Standard API.

[DelphineL]

So if I understand your comment, you mean that I can write several channels in an asynchronous tdms, but I cannot garrantee that data on channel 1 will always be written in the first column of the file?

For now, I have duplicated tdms files and FIFOs, but not the initialization of the fpga vi and the start. But I have underflow problems (error 50400).

Also I know that the fpga vi will execute the two loops in parallel, but how to be sure that it will be the same in the host?

[deppSu]

The data on channel 1 should be written in the first column, otherwise it can't be called channel 1, right?

TDMS advanced API could produce same data layout as TDMS standard API. The key point is to understand how to use it.

I recommand you reading demns comments:

"

http://zone.ni.com/reference/en-XX/help/371361J-01/glang/tdms_set_channel_info/

Basically you call that VI <N> times with the configuration you plan on giving the TDMS file. For example, if you want to write 7 doubles that all belong to the same channel, then 8 I64s that alternate between chA and chB, you would call that function twice with these parameters:

{"non interleaved"; "Group Name", ["Ch 0"], <double>, 7}

and

{"interleaved";"Group Name", ["Ch A", "Ch B"], <I64>, 4}

All you're doing is setting metadata that the TDMS file will hold on to, and when you write to the file its going to interpret the data you send in, in that exact order, in that exact way.

"

[DelphineL]

Thank you DeppSu for your explanation, I will look into that.

But first, I want to be sure that the FPGA and the Hot general designs are correct, which for the moment I am not sure. So I have included my code.

I tried the Host vi several times, and it seems that it works sometimes and sometimes not, like there are some communication problems between the fpga and the host on the "read acquire region" method which is not executed. I managed to make it work randomly before, but not now. Maybe it is because of the reset that I added?

If someone could check my code and help me, I would really appreciate it since nobody in my workplace has the expertise to do so 🙂 If you see some obvious mistake, please share with me, I also added some comment boxes in the code with questions.

Delphine

[DelphineL]

Small precision,

The acquire read region seems to wait for data from the fpga since i have put a timeout of -1. But I don't know why it does not find any data since the fpga acquires normally a lot faster. So it maybe that the fpga is not started, but why?

[Craig_]

Applicable: http://www.ni.com/product-documentation/53547/en/