High Speed Clock Signal Generation Using FPGA Ouput

[Adarsh]

Hi,

This a screen shot of a LabVIEW FPGA program. Here I am trying to generate 5MHz Clock signal at Connector 0 DIO12. But I get around 2MHz when I measure the signal using an oscilloscope. Would some tell me what’s wrong ?

LabVIEW 2011

FPGA Target  : PXI 7841

I set DIO 12 to Nerver Arbitrate in the property setting.

[Intaris · Accepted solution]

You are reading in one port, negating it and sending it back out over the same port?

You know you can have some delays in there, right?  Your output value on the DIO output doesn't instantly mirror on the input.  I've done things like this in the past (at 40MHz) and the delay (depending on the hardware being used) can be several cycles.

Try replacing the DIO Read with a simple shift register negating the boolean and using the HDIO12 purely as an output.

[Adarsh]

Thank you for the reply!

As it’s an FPGA output I was assuming that there is no delay in updating i/o(it’s a routing right?). I will try the method you suggested.

Thank you

Adarsh

[Adarsh]

Its working. Thank you!

[Hooovahh]

I'm not certain but maybe some of the delay is happening because you are changing the mode of the pin.  According to the specs on the card it is capable of having a Maximum Clock Rate of 40MHz under the DIO section.  So if you are purely doing digital reads, or digital writes you should be able to update/read 40,000,000 times a second.  If you perform a read, which can take up to 1/40M of a second, then invert which takes some time but practically none, then another write which can take up to 1/40M of a second, your loop rate should still be faster than the 10MHz you showed.  That's why I suspect there is time involved in changing over the pin from a read mode to a write.

If you try to do something similar with the analog you'll notice the maximum update rate is only 1MHz.  So while your logic and code can run at 40MHz you can only update the analog value at 1MHz.  Because of this in the past I have had two loops.  One running a at the maximum clock rate doing the logic calculations, and then sending the result to another loop that updates the output at the maximum rate which in the case of an analog out is only 1MHz.

[Adarsh]

It makes sense, I appreciate your information. Thank you!

Adarsh