FPGA

[alre]

Hello,

I have read that " You can not use LabVIEW classes in a top-level FPGA VI ". What does the "top-level FPGA VI" mean?

best regard

[Hooovahh · Accepted solution]

The Top Level VI, is the VI that is called by no VI, as a subVI (except reentrant ones I guess).  It is the one that starts the execution.

http://www.ni.com/documentation/en/labview-comms/1.0/fpga-targets/designating-top-level-fpga-vi/

Also you need a more descriptive title post, and to use search next time.

[alre]

Thanks for your reply!

[Dragis · Accepted solution]

Just to expand on Hoovahh's response a bit ...

The FPGA context currently only allows one VI to represent the image for the entire FPGA. That VI is determined by the Build Specification. You can see which VI is selected as Top-Level in the Build Specification's Properties page. 

Good luck!

[alre]

Thanks!!!

[JZWare]

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@alre wrote:

Hello,

I have read that " You can not use LabVIEW classes in a top-level FPGA VI ". What does the "top-level FPGA VI" mean?

best regard

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Others have answered what a "top-level FPGA VI" is.  What I want to address is your first statement: "You can not use LabVIEW classes in a top-level FPGA VI".

I don't know what was meant in the context of what you read but one can definitely instantiate LabVIEW objects in the block diagram of a top-level FPGA VI. Perhaps they meant "you cannot use a class's member method as a top-level FPGA VI"?