05-05-2014 11:12 AM - edited 05-05-2014 11:32 AM
hi
I'm using 2 target to host DMA FIFOs to transfer acquired data to the host PC (see picture).
In the FPGA vi, whitin the while loop, I use a Wait (in microseconds).
Whatever the value "dt" given to this Wait, in the host I recollect data with a systematic error in time:
every 10 points the time elapsed is not dt but (dt+1 microsec).
It's a small error, but becomes significant when dt needs to go below 10 us, as I need, and makes the analysis harder.
This behavior is always identical and not random (I get ten good "dt", then one dt+1 microsec, and back again).
I wonder if I do something wrong or if it's an intrisic problem.
Thanks
Solved! Go to Solution.
05-05-2014 01:54 PM - edited 05-05-2014 01:59 PM
You should try using a Sequence Structure:
Per the help documents:
To manage execution rates with the Loop Timer Express VI, place the Loop Timer Express VI in the first frame of a Flat Sequence structure or a Stacked Sequence structure and put the rest of the code in subsequent frames.
EDIT:
You should also note that the first iteration may be off. There is nothing that can be done about this (from what I understand). But after the initial loop, every other execution will follow quite strictly to your timing selected by the Loop Timer Express VI.
05-06-2014 03:41 AM
solved, thanks.
The problem was that I was using the Wait function, instead of the Loop Timer.
Once switched to Loop Timer, using it in the first frame of a sequence structure, the time between points is finally constant.
Thanks