FPGA target VIs show as "bad" when doing a Project mass compile

[BillMe]

LabVIEW 8.5 with LabVIEW FPGA option

If you have FPGA targets in your project and I do a project mass compile, here's what happens:

1) Mass compile completes
2) Status dialog will show all FPGA target VIs as "bad"
3) All FPGA target VIs will need to be saved and recompiled (new bit files created).

End result is my project mass compile costs me a total of ~1.5 hours of waiting (with 4 FPGAs).

Anyone know if this has been reported to R&D? I searched and didn't find this exact problem.

It would be helpful to have the option to skip the FPGA targets when mass compiling to avoid this.

[Captain_Kirby]

Hi Bill@NGC,

I'll can see how that would be very inconvenient. I'll put a product suggestion in to make it easier to mass compile projects with FPGA targets. You can also place a suggestion for this at the link listed below.

Product Suggestion Center

Thanks for bringing this to our attention! We're always looking for ways to make your experience with LabVIEW better.

[dbtestcon]

Not only does it require a recomplile, but it breaks all of my FPGA code.

Any reference to a hardware item (i.e. hardware port 9472 DO/Port 3) becomes disconnected.  YOu have to go throgh each and every FPGA I/O Node and reselect the signal you want. not only is ithis inconvienient, it opens up the whole VI for possible errors if you reselect.

Since FPGA code is so critical that is runs without a hitch, days of retesting must be done to certify the FPGA functionality.

[Captain_Kirby]

Hi dbtestcon,

I did some testing, and I only see the behavior your describing when the VI is opened outside of the Project Explorer. If you simply open an FPGA VI without the project open, the VI does not have any reference to hardware configured for any target, so all the references are broken. If you simply open the VI from the VIs project explorer, all the wires are in place. This same behavior is seen with any FPGA VI opened outside of the project and is unrelated to Mass Compiling.

I may have misunderstood your issue though, so please feel free to clarify or comment on my statements.

Thanks!

[dbtestcon]

No it's pretty weird. Inside of the project, you open the fpga VI and it's ok.  You do a mass compile and it shows the error that the fpga Vi is bad.   After mass compile, you open the fpga VI and all of the wires are broken.

The nodes have the correct connection shown, but until you click on the checkmarked item, it shows as broken.

[Captain_Kirby]

I agree, that is pretty weird. Is this in 8.5 still? I am having a tough time making the same problem occur on my machine. After I mass compile, I have the same indication of a bad VI, but when I open the VI, all the connections are still there without any broken wires (jus a broken run arrow.) Could you post a simple project and FPGA VI that has this same behavior? I'll see if something fishy is going on in it.

[dbtestcon]

LV8.6

Contact me directly and I can provide the project.

[Captain_Kirby]

Hi,

I understand the need to keep your work private. Its probably best at this point to go ahead and get some direct support since I'm not entirely sure this is a bug. I would go ahead and make a service request with NI. That way, you'll have a single engineer working on your issue and we can find out for certain if this is a bug.