FPGA synchronisation of I/O-Node and variable values / 1 ms delay problem

[Christoph_D]

Hi Intaris,

I think you are absolutely right. I totally forgot to consider the delay of the Delta-Sigma module. Embarrasing.

@MS_Sitec

If you want to have the signals synchronously you have to delay the signals with a smaller delay so the input delay is compensated.

Best regards,

Christoph

[Intaris]

There's no embarrassment neccessary.  Given the amount of things we need to take into consideration when pondering such questions, it's no wonder that the occasional fact slips through the cracks.

Comparing signals with different origins (On-FPGA and Off-FPGA) is always a bit more complicated.

[Christoph_D]

Very kind

Nevertheless something that really should be obvious. The expression which came to my mind, when I read your remark (which should be the English equivalent from the German one): the scales fell from my eyes

Thank you for your help!

[Intaris]

Wir können uns auch direkt auf Deutsch unterhalten wenn's besser passt.

[MS_Sitec]

Many thanks to all!

My quick check program test failed because of the dependencies with the SPS.

But I´m sure the input delay as mentioned by Intaris is the reason (= 0.78 ms @ 50 kHz). Through it is a constant value I try to compensate it in software.

MS