FPGA sync or clock out of subVI

[maherhome]

Hi, 

I have an FPGA subVI that watches for two events.  I want to output some sort of trigger from the subVI as I need to trigger other (sub)VIs when those events occur.  This implies I can't pass occurances out of my subVI.  I'm hesitant to use global variables because lots of folks seem down on globals.  I guess I could output boolean wires indicating event occurences but seems a waste to pass those to another VI which would need a sampling loop to watch for changes in the lines (which introduces more jitter).

Any implementation suggestions?

Thanks,

Steve

[MarcoMauri]

If your subvi is the only one writing to the global, then it will be safe to use it to send the trigger to the main vi (no race conditions can occour - provided they don't happen IN the subvi).

As an alternative you can use a FIFO (http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_transfer_data/).

Regards,

Marco

[maherhome]

Can I have multiple (global var) readers without race conditions as long as there's a single writer?  And the readers can be "anywhere" (main VI, other subVIs)?

Steve

[MarcoMauri]

If there's a single writer you cannot have race conditions.

Here's a tutorial on locals, Globals and race conditions:

http://www.ni.com/white-paper/7585/en

And yes, you can place the global both in the main VI and in the subVIs of your FPGA project.

Regards,

Marco

[Dragis · Accepted solution]

From your description, I believe occurrences are what you want. Like you mentioned, you can't create them in a subVI that is also going to be doing the triggering because dataflow would then not allow the downstream code to execute. However, if you create the occurrence outside the subVIs and then wire them to one subVI to trigger the occurrence and one (or more) to wait for the occurrence you'll avoid having to use globals and keep the scope of the occurrence at the appropriate level.