FPGA startup timing and ADC sampling rate

[stefanrasch]

Hello,

I have two Questions concerning the behaviour of the LabView FPGA Code (on CRio 7852R).

1. I have two parallel While-Loops as the base of my programm. There are no start conditions.

Are they executed in the exact same moment? I need them to be executed perfectly synchron. (Given that they take the same clock cycles to execute)

2. I have a While loop where only values from a ADC are read and saved in a register. Also i'm counting the cylces each loop needs. It executes at 808kHz, where the ADC should only run with 750kHz? What exactly happens there?

Thanks for your help,

Stefan

[SuperDuperCooper]

1. I think so. Another loop can trigger the start times with the 'occurence' block.

2. In my experience with R-series RIOs, if the timing of the ADCs is not regulated, it will run a little faster than its stated maximum, which is what you are seeing. Simplest solution is to regulate to whatever timing you want with the 'loop timer' express vi.

Cheers

[SimonHofmann]

Dear Stefan

Good news! there exist some whitepapers for your problem 😃

to 1.)

Parallel Execution
http://www.ni.com/white-paper/3749/en/#toc2

to 2.)

i would suggest you use these architecture for your FPGA loop design:

Using Single-Cycle Timed Loops to Optimize FPGA VIs (FPGA Module)
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/using_sctl_optimize_fpga/

Best Regards

Simon Hofmann

[stefan__r]

Thanks for your answers.

Those whitepapers would have saved me a lot of thinking time. (Labeling the sctl condition terminal to true is awesome and simple...feel like an idiot for not thinking of it.)