I am thinking about creating a library of reusable host subvi for fpga application. To communicaiton with the FPGA VI, the host vi would contain a FPGA reference, and it is generally a good practice to make that a type def (is that correct?). When I create a reusable subvi, the reference input will not be a type def, and when I feed a type def into the terminal, I will get a coercion. Is that the only way?
------------------------------------------------------------------
Kudos and Accepted as Solution are welcome!