FPGA reference typedef not updated in class private data

[GregFreeman]

I have an FPGA reference linked to a typedef which is passed into a LVOOP object. If I change the FPGA from simulated on dev computer to using the actual hardware, all references to the typedef are updated which are controls on a block diagram. But, the typedef in my class private data seems to not update, so I get broken wires until I replace the control in my class's private data with one copied from my block diagram. Has anyone seen this? Is there a CAR already? I can create a small project to reproduce if need be.

Edit: this also seems to happen when I change bitfiles or change from opening a VI to opening a bitfile in the configure open FPGA VI dialog.

[JoeySpinella]

Hi Greg,

We do not appear to have documented this issue as a CAR.

If you are able to, please post a small project that reproduces this issue so that I can validate it and file a CAR.

Thanks!

[GregFreeman]

Here is a project the reproduces the issue. Open RT Main and you will notice there is no broken run arrow. Now Configure Open VI Reference and change it to bitfile. You will see that the wire on the RT Main block diagram going into the subVI doesn't break, showing the control updated on the front panel of the subVI like it should. But, you will have a broken run arrow and if you open that subVI you'll see the wire into the bundle function on the subVIs block diagram is now broken. This broken wire goes away once you open the class's private data and replace the control, but in my opinion that should update just like the control on the front panel did. 

Let me know if you have any questions. Also, before you start, you may have to update the path to the typedef in the Configure FPGA VI reference since it is an absolute path. I don't know if it updates relatively once you put it on your PC. 

[JoeySpinella · Accepted solution]

Hi Greg,

I was able to reproduce your issue thanks to your easy to follow instructions.

I noticed that the type def does successfully update thanks to checking "Bind FPGA host reference to type definition" in the Configure Open FPGA VI Reference. What does not automatically update is the OOP Issue.ctl, which has a nested reference to the type def in the private data.

The fastest workaround I could find was to right click on "Issue.ctl" in the project and click Save. This immediately fixed the broken error wire.

While the Configure Open FPGA VI Reference has the convenient ability to bind to the type def, it does not broadcast that change to the class's private data. I would not call this a bug, but I can see how you would like it to work that way.

I would recommend you post this on the Idea Exchange (I can see that you are already regular there).

[GregFreeman]

Thanks, Joey. The save is probably a sufficient work around for now. Better than always copying and pasting the updated typedef into the class's private data. Thanks for looking into this.