FPGA read write control node changing unrelated control when built and run as a startup rtexe

[AbandoningCausality]

I'm targeting a CRIO 9066. Running LabVIEW RT 2015SP1. My application works well when run from the development environment but when I build it and run it as a startup exe I noticed some odd behavior. I was able to trace it down to one node

That's writing 1 into the previous control (I8)

That is, samples should be 9 but if I execute the request node (FYI, it's a latching boolean, I don't know if that's relevant), samples becomes 1.

This only happens when run as an RT executable.  Any ideas or suggestions to prevent random errors like this?

Other details which may or may not be relevant:

Open FPGA reference opens the build spec (not a bitfile or VI)

Open FPGA ref is in a functional global that is used in multple places:

[Kelle]

could you provide a bit more code regarding where the 1 sample is being written vs the 9 that is expected?  I'm not really getting what is going on in your code

[AbandoningCausality]

Sure,

Here's the equivalent code:

In development mode, I get a 9 out. When I compile, I get 1 out. Samples is used only once in the FPGA as a control.