FPGA "Mean, Variance & Standard Dev" VI

[alchmcknzie]

Hi Everyone,

I'm using the "Mean, Variance & Standard Deviation" express VI to average 130 samples of a given signal.  When I run the program the "Output Valid" boolean is always false.  What does this mean exactly?  The output looks valid... The documentation for this VI is fairly poor.  Can anyone explain what that output is telling me?

Thanks!

   -Alec

[JLewis]

Since the VI operates on "frames" of data, that output goes true on the call when the output corresponding to the previous frame of data first becomes available. Then it goes false, waiting for the next frame to complete. You won't see it if your loop is running too fast--it's intended for programmatic use to allow downstream logic to know when new results come in. The results are internally registered, so that's why the output always looks valid. If you're just monitoring results on a front panel, you might not care about the valid signal.

Could you provide some specifics on what you would like the documentation to say?

Thanks,

Jim

[alchmcknzie]

Hi Jim,

Thanks for the response!  Maybe I'm misunderstanding the purpose of the VI.

What I'm trying to do is take a running average - i.e. everytime the loop executes I want the VI to output the average of the previous 130 iterations.  Normally I'd store all the data in an 130 element array, have every new sample kick out an old one and then average the array values.  This is how I understood the "Mean, Variance & Standard Deviation" VI to work.  Is this correct?

On the front panel of the attached block diagram above, the boolean is always FALSE.  I can't visably see it go TRUE.  Does that mean the VI waits for 130 samples and then goes true for one iteration?

When I say the documentation is weak, I mean the basic functionality of the VI is not explained well and there are no examples available.

-Alec

[JLewis · Accepted solution]

Hi Alec,

OK, I see the source of confusion now. This VI does not support running averages--it is what we have been referring to as "frame-based", producing a single measurement result for each 130 incoming samples, and a single pulse of the data valid output for each 130 samples. This mode of operation is analogous to the array-based VIs (Mean.vi, etc.) in the Mathematics>>Probability and Statistics palette, which take an array in and output a scalar. The only difference is on the FPGA we need to stream in the array one point at a time. What you were expecting (a reasonable expectation) is analogous to the Mean PtbyPt.vi that takes in a scalar input and updates the mean result on every call. We implemented the frame-based version first because it avoids the need to store the entire array. To see exactly what we do on any of these VIs, just right-click on the node and select "Convert to SubVI", where you can view and/or modify the code to suit your needs.

For an example showing a similar mode of operation, you can check out the Analog Period Measurement example (examples\R Series\FPGA Fundamentals\Analysis and Control\Period Measurement). That example shows some external logic added to latch the result for each period measurement--as you've already observed, that isn't necessary for Mean, Variance & Standard Deviation since that latching is done internally.

If the documentation clearly explained the behavior above, would that meet your needs or is there anything else you would expect it to cover?

I'll submit corrective action requests on the lack of an example and the clarifying documentation.

Thanks for the feedback!

Jim

[dreeves73]

Hi Jim,

The help still has not been updated in LV2018. What you've explained clears things up though. I was under the same impression as Alec - i.e. it was a running average.